RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM
Test Circuits and Waveforms
VDS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
RG
VGS
DUT
+
VDD
-
tP
0V
IAS
0
0.01Ω
tP
IAS
BVDSS
VDS
VDD
tAV
FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 13. UNCLAMPED ENERGY WAVEFORMS
RGS
RL
DUT
+
VDD
-
VGS
FIGURE 14. SWITCHING TIME TEST CIRCUIT
VDS
RL
VGS
Ig(REF)
DUT
+
VDD
-
FIGURE 16. GATE CHARGE TEST CIRCUIT
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
FIGURE 15. RESISTIVE SWITCHING WAVEFORMS
VDD
VDS
Qg(TOT)
VGS
VGS = 2V
0
Qg(10)
Qg(TH)
VGS = 10V
VGS = 20V
Ig(REF)
0
FIGURE 17. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM Rev. C