PATENTED
Read-Modify-Write Mode (Successive Address Accessing)
HT1621/HT1621G
CS
WR
RD
D ATA
1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0
M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 1 ) D a ta (M A + 2 )
Command Mode (Command Code : 1 0 0)
CS
WR
D ATA
1 0 0 C8 C7 C6 C5 C4 C3 C2 C1 C0
C8 C7 C6 C5 C4 C3 C2 C1 C0
C om m and 1
C o m m a n d ...
C om m and i
C om m and
or
D a ta M o d e
Mode (Data and Command Mode)
CS
WR
D ATA
RD
C om m and
or
A d d re s s & D a ta
D a ta M o d e
C om m and
or
A d d re s s a n d D a ta
D a ta M o d e
C om m and
or
A d d re s s a n d D a ta
D a ta M o d e
Note: It is recommended that the host controller should read in the data from the DATA line between the rising edge
of the RD line and the falling edge of the next RD line.
Rev. 2.90
12
November 9, 2010