HT82K94A Ver la hoja de datos (PDF) - Holtek Semiconductor
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componentes Descripción
Fabricante
HT82K94A Datasheet PDF : 43 Pages
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HT82K94E/HT82K94A
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem resets (power-up, WDT time-out or RES reset) or
when the system awakes from the HALT state.
When a system reset occurs, an SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
VDD
RES
S S T T im e - o u t
C h ip R e s e t
tS S T
Reset Timing Chart
V DD
RES
Reset Circuit
The functional unit chip reset status are shown below.
Program Counter 000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/event Counter Off
Input/output Ports Input mode
Stack Pointer
Points to the top of the stack
H A LT
W DT
W a rm R e s e t
RES
O SC1
SST
1 0 - b it R ip p le
C o u n te r
C o ld
R eset
S y s te m R e s e t
Reset Configuration
The status of the registers are summarized in the following table.
Register
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
TMR0
xxxx xxxx 0000 0000 0000 0000 0000 0000
TMR0C
00-0 1000 00-0 1000 00-0 1000 00-0 1000
TMR1H
xxxx xxxx 0000 0000 0000 0000 0000 0000
TMR1L
xxxx xxxx 0000 0000 0000 0000 0000 0000
TMR1C
00-0 1--- 00-0 1--- 00-0 1--- 00-0 1---
Program
Counter
000H
000H
000H
000H
MP0
xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu
MP1
xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu
ACC
xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu
TBLP
xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu
TBLH
-xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu
STATUS
--00 xxxx --1u uuuu --uu uuuu --00 uuuu
INTC
-000 0000 -000 0000 -000 0000 -000 0000
WDTS
1000 0111 1000 0111 1000 0111 1000 0111
PA
1111 1111 1111 1111 1111 1111 1111 1111
PAC
1111 1111 1111 1111 1111 1111 1111 1111
PB
1111 1111 1111 1111 1111 1111 1111 1111
WDT
Time-Out
(HALT)*
USB-Reset USB-Reset
(Normal)
(HALT)
uuuu uuuu
uu-u uuuu
uuuu uuuu
uuuu uuuu
uu-u u---
uuuu uuuu
00-0 1000
uuuu uuuu
uuuu uuuu
00-0 1---
uuuu uuuu
00-0 1000
uuuu uuuu
uuuu uuuu
00-0 1---
000H
000H
000H
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--11 uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--uu uuuu
-000 0000
1000 0111
1111 1111
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--01 uuuu
-000 0000
1000 0111
1111 1111
1111 1111
1111 1111
Rev. 1.50
13
October 11, 2007
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