Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS84327
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
Q0, nQ0 Output
Differential output pair. LVPECL interface levels.
3, 4
Q1, nQ1 Output
Differential output pair. LVPECL interface levels.
5, 6
Q2, nQ2 Output
Differential output pair. LVPECL interface levels.
7, 8
Q3, nQ3 Output
Differential output pair. LVPECL interface levels.
9, 10
Q4, nQ4 Output
Differential output pair. LVPECL interface levels.
11, 12
Q5, nQ5 Output
Differential output pair. LVPECL interface levels.
13, 24
16
14
15
17
18
VCCO
VCC
VEE
PLL_SEL
VCCA
F_SEL2
Power
Power
Input
Power
Input
Pullup
Pullup
Output supply pins.
Core supply pin.
Negative supply pin.
Selects between the PLL and crystal inputs as the input to the dividers.
When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Feedback frequency select pin. LVCMOS/LVTTL interface levels.
19, 20
21
22
XTAL2, XTAL1
MR
F_SEL1
Input
Input
Input
Pulldown
Pulldown
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low, and the inverted
outputs nQx to go high. When logic LOW, the internal dividers and
the outputs are enabled. LVCMOS / LVTTL interface levels.
Output frequency select pin. LVCMOS/LVTTL interface levels.
23
F_SEL0
Input Pullup Output frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
R
PULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KW
KW
84327AM
www.icst.com/products/hiperclocks.html
2
REV. A SEPTEMBER 18, 2003