IDT70V16S Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT70V16S Datasheet PDF : 18 Pages
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ELIMINARY
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
70V16/5X15
Com'l Ony
70V16/5X20
Com'l
& Ind
70V16/5X25
Com'l Only
Symbol
Parameter
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
Min. Max. Min. Max. Min. Max. Unit
____
15
____
20
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20
ns
tBAC
BUSY Ac cess Time from Chip Enable LOW
____
15
____
20
____
20
ns
tBDC
BUSY Disable Time from Chip Enable HIGH
tAPS
Arbitration Priority Set-up Time(2)
____
15
____
17
____
17
ns
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
tWH
Write Hold After BUSY(5)
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
____
18
____
30
____
30
ns
12
____
15
____
17
____
ns
0
____
0
____
0
____
ns
12
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
30
____
45
____
50
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
25
____
35
____
35
ns
5669 tbl 13
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
DATAIN "A"
ADDR"B"
BUSY"B"
tAPS (1)
tDW
VALID
MATCH
tDH
tBDA
tBDD
tWDD
DATAOUT "B"
tDDD (3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL.
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
VALID
5669 drw 12
6.1412
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