IDT70V16S Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT70V16S Datasheet PDF : 18 Pages
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HIGH-SPEED 3.3V
16/8K X 9 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70V16/5S/L
.eatures
x True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x High-speed access
– Commercial:15/20/25ns (max.)
– Industrial: 20ns (max.)
x Low-power operation
– IDT70V16/5S
Active: 430mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V16/5L
Active: 415mW (typ.)
Standby: 660µW (typ.)
x IDT70V16/5 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
x M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
x Busy and Interrupt Flag
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x LVTTL-compatible, single 3.3V (+0.3V) power supply
x Available in 68-pin PLCC and an 80-pin TQFP
x Industrial temperature range (–40°C to +85°C) is available
for selected speeds
.unctional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O8L
BUSYL(2,3)
A13L(1)
A0L
I/O
Control
I/O
Control
Address
Decoder
14
CEL
OEL
R/WL
MEMORY
ARRAY
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL(3)
M/S
NOTES:
1. A13 is a NC for IDT70V15.
2. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
1
©2002 Integrated Device Technology, Inc.
Address
Decoder
CER
OER
R/WR
I/O0R-I/O8R
BUSYR(2,3)
A13R(1)
A0R
SEMR
INTR(3)
5669 drw 01
AUGUST 2002
DSC 5669/1
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