IDT72V36110L7-5BBI Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT72V36110L7-5BBI

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO

Integrated Device Technology 

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

65,536 x 36 and 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

OPTIONAL CONFIGURATIONS

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting together the control

signals of multiple devices. Status flags can be detected from any one device.

The exceptions are the EF and FF functions in IDT Standard mode and the IR

and OR functions in FWFT mode. Because of variations in skew between RCLK

and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary

by one cycle between FIFOs. In IDT Standard mode, such problems can be

avoided by creating composite flags, that is, ANDing EF of every FIFO, and

separately ANDing FF of every FIFO. In FWFT mode, composite flags can be

created by ORing OR of every FIFO, and separately ORing IR of every FIFO.

Figure 29 demonstrates a width expansion using two IDT72V36100/

72V36110 devices. D0 - D35 from each device form a 72-bit wide input bus and

Q0-Q35 from each device form a 72-bit wide output bus. Any word width can

be attained by adding additional IDT72V36100/72V36110 devices.

PARTIAL RESET (PRS)

MASTER RESET (MRS)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

RETRANSMIT (RT)

DATA IN

m+n

D0 - Dm m

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

(1)

GATE

FULL FLAG/INPUT READY (FF/IR) #1

FULL FLAG/INPUT READY (FF/IR) #2

PROGRAMMABLE (PAF)

HALF-FULL FLAG (HF)

Dm+1 - Dn

n

IDT

72V36100

72V36110

FIFO

#1

m

READ CLOCK (RCLK)

IDT

72V36100

72V36110

READ ENABLE (REN)

OUTPUT ENABLE (OE)

PROGRAMMABLE (PAE)

FIFO

#2

EMPTY FLAG/OUTPUT READY (EF/OR) #1

EMPTY FLAG/OUTPUT READY (EF/OR) #2

n Qm+1 - Qn

m+n

DATA OUT

(1)

GATE

Q0 - Qm

6117 drw34

NOTES:

1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.

2. Do not connect any output control signals directly together.

3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.

Figure 29. Block Diagram of 65,536 x 72 and 131,072 x 72 Width Expansion

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