IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
CLKB
CSB
W/RB
MBB
ENB
B0 - B35
tENS1
tENS1
tENS2
tENH
tENH
tENH
tENS2
tENH
tDS
tDH
W1
COMMERCIAL TEMPERATURE RANGE
CLKA
MBF2
tPMF
CSA
tPMF
W/RA
MBA
ENA
A0 - A35
tENS2
tENH
tEN
tMDV
FIFO2 Output Register
tPMR
tDIS
W1 (Remains valid in Mail 2 Register after read)
4679 drw 24
Figure 21. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
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