IDT72V36102 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT72V36102 Datasheet PDF : 29 Pages
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IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant)
Symbol
tA
tPIR
tPOR
tPAE
tPAF
tPMF
tPMR
tMDV
tPRF
tEN
tDIS
Parameter
Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to
FFB/IRB
Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to
EFB/ORB
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
Propagation Delay Time, CLKA↑ to B0-B35(1) and
CLKB↑ to A0-A35(2)
Propagation Delay Time, MBA to A0-A35 valid and
MBB to B0-B35 Valid
Propagation Delay Time, RST1 LOW to AEB LOW, AFA
HIGH, and MBF1 HIGH, and RST2 LOW to AEA LOW,
AFB HIGH, and MBF2 HIGH
Enable Time, CSA and W/RA LOW to A0-A35 Active
and CSB LOW and W/RB HIGH to B0-B35 Active
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance
and CSB HIGH or W/RB LOW to B0-B35 at high-impedance
IDT72V3682L10
IDT72V3692L10
IDT72V36102L10
Min.
Max.
2
6.5
2
6.5
1
6.5
1
6.5
1
6.5
0
6.5
2
8
2
6.5
1
10
2
6
1
6
IDT72V3682L15
IDT72V3692L15
IDT72V36102L15
Min.
Max.
Unit
2
10
ns
2
8
ns
1
8
ns
1
8
ns
1
8
ns
0
8
ns
2
10
ns
2
10
ns
1
15
ns
2
10
ns
1
8
ns
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
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