IDT79R3081-33 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT79R3081-33 Datasheet PDF : 38 Pages
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IDT79R3081 RISController
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS R3081
COMMERCIAL TEMPERATURE RANGE (1, 2) (50MHz)— (TC = 0°C to +85°C, VCC = +5.0V ±5%)
50MHz
Symbol
Signals
t1
BusReq, Ack, BusError,
t1a
A/D
t2
BusReq, Ack, BusError,
t2a
A/D
t3
A/D, Addr, Diag, ALE, Wr
t4
A/D, Addr, Diag, ALE, Wr
t5
BusGnt
t6
BusGnt
t7
Wr, Rd, Burst/WrNear, A/D
t8
ALE
t9
ALE
Description
Set-up to SysClk rising
RdCEn, CohReq
Set-up to SysClk falling
Hold from SysClk rising
RdCEn, CohReq
Hold from SysClk falling
Tri-state from SysClk rising
Burst/WrNear, Rd, DataEn
Driven from SysClk falling
Burst/WrNear, Rd, DataEn
Asserted from SysClk rising
Negated from SysClk falling
Valid from SysClk rising
Asserted from SysClk rising
Negated from SysClk falling
Min.
5
6
4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
10
10
7
7
5
4
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t10
A/D
Hold from ALE negated
1.5
—
ns
t11 DataEn
Asserted from SysClk falling
—
15
ns
t12 DataEn
Asserted from A/D tri-state(3)
0
—
ns
t14
A/D
Driven from SysClk rising(3)
0
—
ns
t15
Wr, Rd, DataEn, Burst/WrNear Negated from SysClk falling
—
6
ns
t16
Addr(3:2)
Valid from SysClk
—
6
ns
t17
Diag
Valid from SysClk
—
11
ns
t18
A/D
Tri-state from SysClk falling
—
10
ns
t19
A/D
SysClk falling to data valid
—
12
ns
t20
ClkIn (2x clock mode)
Pulse Width HIGH
N/A (8)
ns
t21
ClkIn (2x clock mode)
Pulse Width LOW
N/A (8)
ns
t22
ClkIn (2x clock mode)
Clock Period
N/A (7, 8)
ns
t23
Reset
Pulse Width from VCC valid
200
—
µs
t24
Reset
Minimum Pulse Width
32
—
tsys
t25
Reset
Set-up to SysClk falling
5
ns
t26
Int
Mode set-up to Reset rising
9
—
ns
t27
Int
Mode hold from Reset rising
0
—
ns
t28
SInt, SBrCond
Set-up to SysClk falling
5
—
ns
t29
SInt, SBrCond
Hold from SysClk falling
3
—
ns
t30
Int, BrCond
Set-up to SysClk falling
5
—
ns
t31
Int, BrCond
Hold from SysClk falling
3
—
ns
tsys
SysClk (full frequency mode) Pulse Width(5)
N/A (8)
N/A (8)
ns
t32
SysClk (full frequency mode) Clock HIGH Time(5)
N/A (8)
N/A (8)
ns
t33
SysClk (full frequency mode) Clock LOW Time(5)
N/A (8)
N/A (8)
ns
NOTES:
2889 tbl 11
1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.
2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.
3. Guaranteed by design.
4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
5. In 1x clock mode, t22 is replaced by t44/2.
6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns, 3ns for 40MHz and 50MHz.
7. When using the Reduced Frequency feature, the minimum allowed internal CPU speed is 0.5 MHz.
8. For the 50MHz version, 1x Clock Mode and half-frequency bus mode only.
5.5
20
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