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LM3S608-IQC20-B0 Datasheet PDF : 416 Pages
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LM3S608 Microcontroller
10.5 Register Descriptions .............................................................................................................. 200
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.3.1
11.3.2
11.4
11.5
Analog-to-Digital Converter (ADC) ................................................................................. 221
Block Diagram ........................................................................................................................ 222
Functional Description ............................................................................................................. 222
Sample Sequencers ................................................................................................................ 222
Module Control ........................................................................................................................ 223
Hardware Sample Averaging Circuit ......................................................................................... 224
Analog-to-Digital Converter ...................................................................................................... 224
Test Modes ............................................................................................................................. 224
Internal Temperature Sensor .................................................................................................... 224
Initialization and Configuration ................................................................................................. 225
Module Initialization ................................................................................................................. 225
Sample Sequencer Configuration ............................................................................................. 225
Register Map .......................................................................................................................... 226
Register Descriptions .............................................................................................................. 227
12 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 254
12.1 Block Diagram ........................................................................................................................ 255
12.2 Functional Description ............................................................................................................. 255
12.2.1 Transmit/Receive Logic ........................................................................................................... 255
12.2.2 Baud-Rate Generation ............................................................................................................. 256
12.2.3 Data Transmission .................................................................................................................. 257
12.2.4 FIFO Operation ....................................................................................................................... 257
12.2.5 Interrupts ................................................................................................................................ 257
12.2.6 Loopback Operation ................................................................................................................ 258
12.3 Initialization and Configuration ................................................................................................. 258
12.4 Register Map .......................................................................................................................... 259
12.5 Register Descriptions .............................................................................................................. 260
13 Synchronous Serial Interface (SSI) ................................................................................ 292
13.1 Block Diagram ........................................................................................................................ 292
13.2 Functional Description ............................................................................................................. 292
13.2.1 Bit Rate Generation ................................................................................................................. 293
13.2.2 FIFO Operation ....................................................................................................................... 293
13.2.3 Interrupts ................................................................................................................................ 293
13.2.4 Frame Formats ....................................................................................................................... 294
13.3 Initialization and Configuration ................................................................................................. 301
13.4 Register Map .......................................................................................................................... 302
13.5 Register Descriptions .............................................................................................................. 303
14 Inter-Integrated Circuit (I2C) Interface ............................................................................ 329
14.1 Block Diagram ........................................................................................................................ 329
14.2 Functional Description ............................................................................................................. 329
14.2.1 I2C Bus Functional Overview .................................................................................................... 330
14.2.2 Available Speed Modes ........................................................................................................... 332
14.2.3 Interrupts ................................................................................................................................ 333
14.2.4 Loopback Operation ................................................................................................................ 333
14.2.5 Command Sequence Flow Charts ............................................................................................ 334
14.3 Initialization and Configuration ................................................................................................. 340
14.4 I2C Register Map ..................................................................................................................... 341
October 01, 2007
5
Preliminary
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