LPC47M14G-NC Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47M14G-NC

128 Pin Enhanced Super I/O Controller with an LPC Interface and USB Hub

SMSC -> Microchip 

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset

and it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

PS/2 Model 30 Mode

7

6

nDRV2 nDS1

RESET N/A

1

COND.

5

nDS0

1

4

WDATA

F/F

0

3

RDATA

F/F

0

2

WGATE

F/F

0

1

nDS3

1

0

nDS2

1

BIT 0 nDRIVE SELECT 2

The DS2 disk interface is not supported.

BIT 1 nDRIVE SELECT 3

The DS3 disk interface is not supported.

BIT 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is

cleared by the read of the DIR register.

BIT 3 READ DATA

Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is

cleared by the read of the DIR register.

BIT 4 WRITE DATA

Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and

is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface output.

BIT 7 nDRV2

Active low status of the DRV2 disk interface input. Note: This function is not supported.

DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the

DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be

written to at any time.

RESET

COND.

7

MOT

EN3

0

6

MOT

EN2

0

5

MOT

EN1

0

4

MOT

EN0

0

3

2

DMAEN nRESET

0

0

1

DRIVE

SEL1

0

0

DRIVE

SEL0

0

SMSC DS – LPC47M14X

Page 29

Rev. 03/19/2001

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