LTC1277CSW Ver la hoja de datos (PDF) - Linear Technology

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LTC1277CSW

12-Bit, 10mW, 100ksps ADCs with 1µA Shutdown

Linear Technology 

LTC1274/LTC1277

APPLICATI S I FOR ATIO

Figure 8. For bipolar mode, a 0.1µF ceramic provides

adequate bypassing for the VSS pin. The capacitors must

be located as close to the pins as possible. The traces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

Input signal leads to AIN and signal return leads from

AGND (Pin 3 for LTC1274, Pin 4 for LTC1277) should be

kept as short as possible to minimize input noise cou-

pling. In applications where this is not possible a shielded

cable between source and ADC is recommended.

Also, since any potential difference in grounds between

the signal source and the ADC appears as an error voltage

in series with the input signal, attention should be paid to

reducing the ground circuit impedances as much as

possible.

A single point analog ground separate from the logic

system ground should be established with an analog

ground plane at AGND or as close as possible to the ADC.

DGND (Pin 12) and all other analog grounds should be

connected to this single analog ground point. No other

digital grounds should be connected to this analog ground

point. Low impedance analog and digital power supply

common returns are essential to low noise operation of

the ADC and the foil width for these tracks should be as

wide as possible. In applications where the ADC data

outputs and control signals are connected to a continu-

ously active microprocessor bus, it is possible to get

errors in conversion results. These errors are due to

feedthrough from the microprocessor to the successive

approximation comparator. The problem can be elimi-

nated by forcing the microprocessor into a Wait state

during conversion or by using three-state buffers to

isolate the ADC data bus. Figure 9 is a typical application

circuit for the LTC1274.

ANALOG

INPUT

CIRCUITRY

1

AIN

AGND

+

3

–

VREF

2

LTC1274

AVDD DVDD DGND

24 17 12

10µF

0.1µF

10µF

0.1µF

DIGITAL

SYSTEM

GROUND CONNECTION

TO DIGITAL CIRCUITRY

ANALOG GROUND PLANE

LTC1274/77 • F08

Figure 8. Power Supply Grounding Practice

14

2.42V

VREF OUTPUT

+

10µF

LTC1274

ANALOG INPUT

(0V TO 4.095V)

0.1µF

1

2 AIN

3 VREF

AGND

4

D11 (MSB)

24

VDD 23

VSS 22

BUSY

21

CS

5

D10

6

D9

20

RD

19

CONVST

7

D8

18

SLEEP

12-BIT

PARALLEL

BUS

8

D7

9

D6

10

D5

17

REFRDY

16

D0

15

D1

11

D4

12

DGND

14

D2

13

D3

5V

+

10µF

µP

CONTROL

LINES

0.1µF

CONVERSION START INPUT

SLEEP MODE INPUT

REFERENCE READY SIGNAL

LTC1274/77 • F09

Figure 9. LTC1274 Typical Circuit

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