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LTC6104H

High Voltage, High Side,Bi-Directional Current Sense Amplifier

Linear Technology 

LTC6104

APPLICATIONS INFORMATION

If the maximum output current, IOUT, is limited to 1mA,

ROUT equals 3V/1mA = 3k and RIN = 3k/6 – 0.3Ω (internal

device resistance) = 499.7Ω.

The output error due to DC offset is ±510µV (typ) and

the error due to offset current, IOS, is 3k • 100nA =

300µV(typ).

The maximum output error can therefore reach ±810µV

or 0.027% (–71dB) of the output full scale. Considering

the system input 60dB dynamic range (ISENSE = ±1mA to

±1A), the 71dB performance of the LTC6104 makes this

application feasible.

Output Error, EOUT, Due to the Current Mirror Errors,

IOUT-GAINERR and IOUT-OSERR

When VSENSE is negative, amplifier B would be on and

amplifier A off. The output of amplifier B drives an internal

current mirror which is connected to the OUT pin. This

current mirror has some error associated with it, and this

error can be calculated as follows:

IOUT-GAINERR = ±0.2% • IOUT, with IOUT = ±1mA,

IOUT-GAINERR(MAX) = ±2μA

IOUT-OSERR = ±0.2μA

IOUT-ERR(MAX) = IOUT-GAINERR + IOUT-OSERR = ±2μA +

±0.2μA = ±2.2μA

EOUT-ERR(MAX) = IOUT-ERR(MAX) • ROUT

The combined effect of amplifier offset and current mirror

errors is shown graphically in Figure 4.

100

RIN = 100Ω

ROUT = 5k

10

MAXIMUM

1

0.1 TYPICAL

0.01

–500

–300

–100 100

VSENSE (mV)

300 500

6104 F04

Figure 4. Output Error vs Input Voltage

Output Error, EOUT, Due to Trace Resistance

The LTC6104 uses the +INB pin for both the positive “B”

amplifier input and the positive supply input for both

amplifiers. If trace resistance (RT) become significant

(Figure 5), this supply current can cause an input offset

error, which can be calculated as follows:

EOUT(OFFSET)

=

RT

• IS

•

ROUT

RIN

Trace resistances to the –IN terminals will increase the

effective RIN value, causing a gain error (Figure 5). In ad-

dition, internal device resistance will add approximately

0.3Ω to RIN.

Gain error equals:

A V(ERROR)

=

RIN

ROUT

+ RT +

0.3Ω

–

ROUT

RIN

Minimizing resistance in the input traces is important and

care should be taken in the PCB layout. Make the trace

short and wide. Kelvin connection to the shunt resistor

pad should be used. Avoid tapping into this signal along

ILOAD

– VSENSE +

TO

RSENSE

+

CHARGER/LOAD

RIN

RIN

RT

8

+INA

A

VS

RT

RT

RT

7

6

–INA –INB

5

+INB

–+

IS

B

VS

CURRENT

LTC6104 OUT

MIRROR

V–

1

4

+

IOUT

VOUT

–

ROUT

+– VREF

6104 F05

Figure 5. Errors from PCB Traces and Other Parasitic Resistances

6104f

11

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