LH543611 Ver la hoja de datos (PDF) - Sharp Electronics

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Fabricante

LH543611

512 × 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO

Sharp Electronics 

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

AC ELECTRICAL CHARACTERISTICS 1 (VCC = 5 V ± +10%, TA = 0°C to 70°C)

SYMBOL

DESCRIPTION

–18

–20

–25

–30

–35

UNITS

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

fCC

Clock Cycle Frequency

— 55 — 50 — 40 — 33 — 28.5 MHz

tCC

Clock Cycle Time

18 — 20 — 25 — 30 — 35 — ns

tCH

Clock HIGH Time

7 — 8 — 10 — 12 — 15 — ns

tCL

Clock LOW Time

7 — 8 — 10 — 12 — 15 — ns

tDS

Data Setup Time

7.5 — 7.5 — 9 — 10 — 12 — ns

tDH

Data Hold Time

0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

tES

Enable Setup Time

5.5 — 5.5 — 7.5 — 8.5 — 10.5 — ns

tEH

Enable Hold Time

0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

tRWS Read/Write Setup Time

5.5 — 5.5 — 7.5 — 8.5 — 10.5 — ns

tRWH Read/Write Hold Time

0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

tRQS

Request Setup Time

5.5 — 5.5 — 7.5 — 8.5 — 10.5 — ns

tRQH

tAS

tAH

Request Hold Time

Address Setup Time 2

Address Hold Time 2

0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

7.5 — 7.5 — 9 — 10 — 12 — ns

0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

tWSS

tWSH

Width Select Setup Time

Width Select Hold Time 3

5.5 — 5.5 — 7.5 — 8.5 — 10.5 — ns

0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns

tA

Data Output Access Time

— 13 — 13.8 — 16 — 20 — 25 ns

tACK

Acknowledge Access Time

— 9.5 — 9.5 — 13 — 16 — 18 ns

tOH

Output Hold Time

4 — 4 — 4 — 4 — 4 — ns

tZX

Output Enable Time, OE LOW to

D0 – D35 Low-Z 3

1.5

—

1.5

—

2

—

3

—

3

—

ns

tXZ

Output Disable Time, OE HIGH

to D0 – D35 High-Z 3

—

9

—

9

— 12 — 15 — 20 ns

tEF

Clock to EF Flag Valid

— 14 — 14.5 — 19 — 22 — 27 ns

tFF

Clock to FF Flag Valid

— 14 — 14.5 — 19 — 22 — 27 ns

tHF

Clock to HF Flag Valid

— 14 — 14.5 — 19 — 22 — 27 ns

tAE

Clock to AE Flag Valid

— 14.5 — 15 — 19 — 22 — 27 ns

tAF

Clock to AF Flag Valid

— 14.5 — 15 — 19 — 22 — 27 ns

tMBF

Clock to MBF Flag Valid

— 10 — 10 — 13 — 18 — 23 ns

tPF

Data to Parity Flag Valid 4

— 14 — 14 — 17 — 20 — 25 ns

tRS

Reset/Retransmit Pulse Width 5 18 — 20 — 25 — 30 — 35 — ns

tRSS

Reset/Retransmit Setup Time 6 15 — 16 — 20 — 25 — 30 — ns

tRSH

Reset/Retransmit Hold Time 6

7.2 — 8 — 10 — 15 — 20 — ns

tRF

Reset LOW to Flag Valid

tFRL

First Read Latency 7

tFWL

First Write Latency 8

— 21 — 21 — 25 — 30 — 35 ns

18 — 20 — 25 — 30 — 35 — ns

18 — 20 — 25 — 30 — 35 — ns

tBS

Bypass Data Setup

8.5 — 8.5 — 10 — 13 — 15 — ns

tBH

Bypass Data Hold

2 — 2 — 3 — 4 — 5 — ns

tBA

Bypass Data Access

— 15.5 — 16 — 18 — 23 — 28 ns

tSKEW1 Skew Time Read-to-Write Clock 14 — 14.5 – 19 — 22 — 27 — ns

tSKEW2 Skew Time Write-to-Read Clock 14 — 14.5 — 19 — 22 — 27 — ns

NOTES:

1. Timing measurements performed at ‘AC Test Condition’ levels.

2. tAS, tAH address setup times and hold times need only be satisfied at clock edges which occur while the corresponding enables are being as-

serted.

3. Values are guaranteed by design; not currently production tested.

4. Measured with Parity Flag operating in flowthrough mode.

5. When CKA or CKB is enabled; tRS = tRSS + tCH + tRSH.

6. tRSS and/or tRSH need not be met unless a rising edge of CKA occurs while ENA is being asserted, or else a rising edge of CKB occurs while

ENB is being asserted.

7. tFRL is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data.

8. tFWL is the minimum first-read-to-first-write delay, following a full condition, which is required to assure successful writing of data.

10

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