AD1377KD Ver la hoja de datos (PDF) - Analog Devices
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AD1377KD Datasheet PDF : 8 Pages
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AD1376/AD1377
DESCRIPTION OF OPERATION
On receipt of a CONVERT START command, the AD1376/
AD1377 converts the voltage at its analog input into an equiva-
lent 16-bit binary number. This conversion is accomplished as
follows: the 16-bit successive-approximation register (SAR) has
its 16-bit outputs connected both to the device bit output pins
and to the corresponding bit inputs of the feedback DAC. The
analog input is successively compared to the feedback DAC
output, one hit at a time (MSB first, LSB last). The decision to
keep or reject each bit is then made at the completion of each
bit comparison period, depending on the state of the compara-
tor at that time.
GAIN ADJUSTMENT
The gain adjust circuit consists of a 100 ppm/°C potentiometer
connected across ± VS with its slider connected through a
300 kΩ resistor to the gain adjust Pin 29 as shown in Figure 4.
If no external trim adjustment is desired, Pin 27 (offset adj) and
Pin 29 (gain adj) may be left open.
In either adjust circuit, the fixed resistor connected to Pin 27
should be located close to this pin to keep the pin connection
runs short. Comparator Input Pin 27 is quite sensitive to exter-
nal noise pick-up and should be guarded by analog common.
TIMING
The timing diagram is shown in Figure 7. Receipt of a CON-
VERT START signal sets the STATUS flag, indicating conver-
sion in progress. This, in turn, removes the inhibit applied to
the gated clock, permitting it to run through 17 cycles. All the
SAR parallel bits, STATUS flip-flops, and the gated clock in-
hibit signal are initialized on the trailing edge of the CONVERT
START signal. At time t0, B1 is reset and B2–B16 are set uncon-
ditionally. At t1 the Bit 1 decision is made (keep) and Bit 2 is
reset unconditionally. This sequence continues until the Bit 16
(LSB) decision (keep) is made at t16. The STATUS flag is reset,
indicating that the conversion is complete and that the parallel
output data is valid. Resetting the STATUS flag restores the
gated clock inhibit signal, forcing the clock output to the low
Logic “0” state. Note that the clock remains low until the next
conversion.
Corresponding parallel data bits become valid on the same
positive-going clock edge.
Figure 4. Gain Adjustment Circuit (±0.2% FSR)
OFFSET ADJUSTMENT
The zero adjust circuit consists of a 100 ppm/°C potentiometer
connected across ± VS with its slider connected through a
1.8 MΩ resistor to Comparator Input Pin 27 for all ranges. As
shown in Figure 5, the tolerance of this fixed resistor is not
critical, and a carbon composition type is generally adequate.
Using a carbon composition resistor having a –1200 ppm/°C
tempco contributes a worst-case offset tempco of 32 LSB14 ϫ
61 ppm/LSB14 ϫ 1200 ppm/°C = 2.3 ppm/°C of FSR, if the
OFFSET ADJ potentiometer is set at either end of its adjust-
ment range. Since the maximum offset adjustment required is
typically no more than ± 16 LSB14, use of a carbon composition
offset summing resistor typically contributes no more than
1 ppm/°C of FSR offset tempco.
Figure 5. Offset Adjustment Circuit (±0.3% FSR)
An alternate offset adjust circuit, which contributes negligible
offset tempco if metal film resistors (tempco <100 ppm/°C) are
used, is shown in Figure 6.
Figure 7. Timing Diagram (Binary Code
0110011101111010)
DIGITAL OUTPUT DATA
Both parallel and serial data from TTL storage registers is in
negative true form (Logic “1” = 0 V and Logic “0” = 2.4 V).
Parallel data output coding is complementary binary for
unipolar ranges and complementary offset binary for bipolar
ranges. Parallel data becomes valid at least 20 ns before the
STATUS flag returns to Logic “0”, permitting parallel data
transfer to be clocked on the “1” to “0” transition of the STA-
TUS flag (see Figure 8).
Figure 6. Low Tempco Zero Adjustment Circuit
–4–
Figure 8. LSB Valid to Status Low
REV. B
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