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MAX8900B

1.2A Switch-Mode Li+ Chargers with ±22V Input Rating and JEITA Battery Temperature Monitoring

Maxim Integrated 

MAX8900A/MAX8900B/MAX8900C

1.2A Switch-Mode Li+ Chargers with ±22V Input

Rating and JEITA Battery Temperature Monitoring

The guidelines at the top are the most critical:

1) When the step-down converter’s high-side MOSFET

turns on, CINBP delivers a high di/dt current pulse to

INBP. Because of this high di/dt current pulse, place

CINBP close to INBP to minimize the parasitic imped-

ance in the PCB trace.

2) When the step-down converter is increasing the cur-

rent in the inductor, the high-side MOSFET is on and

current flows in the following path: from CINBP into

INBP >> out of LX >> through the inductor >> into CS

>> out of BAT >> through CBAT and back to CINBP

through the ground plane. This current loop should

be kept small and the electrical length from the posi-

tive terminal of CINBP to INBP should be kept short to

minimize parasitic impedance. The electrical length

from the negative terminal of CBAT to the negative

terminal of CINBP should be short to minimize para-

sitic impedance. Keep all sensitive signals such as

feedback nodes or audio lines outside of this current

loop with as much isolation as your design allows.

3) When the step-down converter is decreasing the

inductor current, the low-side MOSFET is on and

the current flows in the following path: out of LX >>

through the inductor >> into CS >> out of BAT >>

through CBAT >> into PGND >> out of LX again. This

current loop should be kept small and the electrical

length from the negative terminal of CBAT to PGND

should be short to minimize parasitic impedance.

Keep all sensitive signals such as feedback nodes or

audio lines outside of this current loop with as much

isolation as your design allows.

4) The LX node voltage switches between INBP and

PGND during the operation of the step-down con-

verter. Minimize the stray capacitance on the LX node

to maintain good efficiency. Also, keep all sensitive

signals such as feedback nodes or audio lines away

from LX with as much isolation as your design allows.

5) In Figure 14, the CS node is connected to the second

layer of metal with vias. Use low-impedance vias that

are capable of handling 1.5A of current. Also, keep

the routing inductor current path on layer 2 just under-

neath the inductor current path on layer 1 to minimize

impedance.

6) Both CBST and CPVL deliver current pulses for the

MAX8900_’s MOSFET drivers. These components

should be placed as shown in Figure 14 to minimize

parasitic impedance.

7) Each of the MAX8900_ bumps has approximately the

same ability to remove heat from the die. Connect as

much metal as possible to each bump to minimize the

BJA associated with the MAX8900_. See the Thermal

Management section for more information on BJA.

In Figure 14, many of the top layer bump pads are con-

nected together in top metal. When connecting bumps

together with top layer metal, the solder mask must

define the pads from 180Fm to 210Fm as shown in

Figure 15. When using solder mask defined pads, please

double check the solder mask openings on the PCB

Gerber files before ordering boards as some PCB lay-

out tools have configuration settings that automatically

oversize solder mask openings. Also, explain in the PCB

fabrication notes that the solder mask is not to be modi-

fied. Occasionally, optimization tools are used at the

PCB fabrication house that modify solder masks. Layouts

that do not use solder mask defined pads are possible.

When using these layouts, adhere to the recommenda-

tions A through G above.

Figure 14. Power PCB Layout Example

32  

Maxim Integrated

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