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MB15F76UL
(Rev.:2001)

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

Jun. 2001

Edition 0.2

MB15F76UL

n PIN DESCRIPTIONS

Pin

No.

Pin

name

I/O

Descriptions

1

fin IF

I

Prescaler input pin for the IF-PLL section.

Connection to an external VCO should be AC coupling.

2

Xfin IF

I

Prescaler complimentary input for the IF-PLL section.

This pin should be grounded via a capacitor.

3

GNDIF

- Ground for the IF-PLL section.

Power supply voltage input pin for the IF-PLL section(except for the

4

VccIF

- charge pump circuit), the shift register and the oscillator input buffer.

When power is OFF, latched data of IF-PLL is lost.

Power saving mode control for the IF-PLL section. This pin must be set

5

PSIF

I at ”L” Power-ON. (Open is prohibited.)

PSIF = ”H” ; Normal mode PSIF = ”L” ; Power saving mode

6

VpIF

- Power supply voltage input pin for the IF-PLL charge pump.

7

DoIF

O

Charge pump output for the IF-PLL section.

Phase characteristics of the phase detector can be reversed by FC-bit.

Lock detect signal output(LD)/ phase comparator monitoring outut

8

LD/fout O (fout). The output signal is selected by a LDS bit in a serial data.

LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal

9

D oR F

O

Charge pump output for the RF-PLL section.

Phase characteristics of the phase detector can be reversed by FC-bit.

10

VpRF

- Power supply voltage input pin for the RF-PLL charge pump.

Power saving mode control for the RF-PLL section. This pin must be

11

PS RF

I set at ”L” Power-ON. (Open is prohibited.)

PSRF = ”H” ; Normal mode PSRF = ”L” ; Power saving mode

12

VccRF

-

Power supply voltage input pin for the RF-PLL section(except for the

charge pump circuit).

13

GNDR F

- Ground for the RF-PLL section.

14

XfinRF

I

Prescaler complimentary input for the RF-PLL section.

This pin should be grounded via a capacitor.

15

finR F

I

Prescaler input pin for the RF-PLL.

Connction to an external VCO should be AC coupling.

Load enable signal input (with the schmitt trigger circuit.)

16

LE

I When LE is set "H", data in the shift register is transferred to the corre-

sponding latch according to the control bit in a serial data.

Serial data input (with the schmitt trigger circuit.)

17

Data

I

A data is transferred to the corresponding latch (IF-ref counter, IF-prog.

counter, RF-ref. counter, RF-prog. counter) according to the control bit

in a serial data.

Clock input for the 23-bit shift register (with the schmitt trigger circuit.)

18

Clock

I One bit data is shifted into the shift register on a rising edge of the

clock.

19

OSCIN

I

The programmable reference divider input. TCXO should be connected

with a AC coupling capacitor.

20

GND

- Ground for OSC input buffer and the shift registor circuit.

3

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