MB90098A Ver la hoja de datos (PDF) - Fujitsu
Número de pieza
componentes Descripción
Fabricante
MB90098A Datasheet PDF : 43 Pages
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MB90098A
(3) Display Signal Timing
Parameter
Dot clock input cycle time
(straight output)
Dot clock input pulse width
(straight output)
Dot clock input cycle time
(demultiplexed output)
Dot clock input pulse width
(demultiplexed output)
Display output control on/off delay
time
Dot clock output delay time 1
Dot clock output delay time 2
Display signal output delay time I1
(straight output)
Display signal output delay time I2
(straight output)
Display signal output delay time O1
(straight output)
Display signal output delay time O2
(straight output)
Display signal output delay time I1
(demultiplexed output)
Display signal output delay time I2
(demultiplexed output)
Display signal output delay time O1
(demultiplexed output)
Display signal output delay time O2
(demultiplexed output)
(VDD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = 0 to 70 °C)
Symbol
Pin
Values
Min. Max.
Unit Remarks
tDIFS DCLKI
10
90
MHz
*1
*3
tDIWHS
tDIWLS
DCLKI
5
ns * 1
5
ns * 3
tDIFD DCLKI
10
140
MHz
*2
*3
tDIWHD
tDIWLD
DCLKI
3
ns * 2
3
ns * 3
tDON DA3 to DA0, VOBA
6
tDOFF DB3 to DB0, VOBB
6
Dot
clock
*4
tPDCS DCLKO
3
6
ns *1
tPDCD DCLKO
3
7
ns *2
tPDIS1
DA3 to DA0, VOBA
DB3 to DB0, VOBB
2
7
ns *1
tPDIS2
DA3 to DA0, VOBA
DB3 to DB0, VOBB
1
6
ns *1
tPDOS1
DA3 to DA0, VOBA
DB3 to DB0, VOBB
−4
5
ns *1
tPDOS2
DA3 to DA0, VOBA
DB3 to DB0, VOBB
−5
4
ns *1
tPDID1
DA3 to DA0, VOBA
DB3 to DB0, VOBB
2
7
ns *2
tPDID2
DA3 to DA0, VOBA
DB3 to DB0, VOBB
1
6
ns *2
tPDOD1
DA3 to DA0, VOBA
DB3 to DB0, VOBB
−5
5
ns *2
tPDOD2
DA3 to DA0, VOBA
DB3 to DB0, VOBB
−6
4
ns *2
*1 : The maximum output frequency for straight output is 90 MHz.
*2 : The maximum output frequency for demultiplexed output is 70 MHz.
*3 : Use a continuous dot clock input signal without interruptions.
*4 : Actual display output varies according to control content, including display output control for each display layer,
display position control, etc.
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