MB91245/S Series
■ HANDLING DEVICES
• Preventing Latch-up
Latch-up may occur in a CMOS IC, if a voltage greater than VCC pin or less than VSS pin is applied to input and
output pin, or if an above-rating voltage is applied between VCC pin and VSS pin. When latch-up occurs, it may
significantly increase the power supply current, and may cause thermal destruction of an element. When you
use a CMOS IC, be very careful not to exceed the maximum rating.
• Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by performing a pull-up or
pull-down with a resistance of 2 kΩ or more. An unused I/O pin should be set to the output status and left open.
When set to the input status, it should be handled in the same way as an input pin.
• About power supply pins
If there are multiple VCC and VSS pins, from the point of view of device design pins to be of the same potential
are connected inside the device to prevent such malfunctioning as latch-up. However, you must connect all the
pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal
operation of strobe signals caused by the rise in the ground level, and to conform to the total output current
rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
Furthermore, it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC
pin and VSS pin near this device.
This device incorporates a regulator. When using the device with 5V power supply, apply that power supply to
the VCC pin and always connect a 1 μF or greater capacitor to the VCC3C pin for the regulator.
• Example of power supply connection
5V
5V
GND
VCC
AVCC
AVRH
AVSS
VSS
VCC3C
1 μF
16