MC100EP131FAR2G Ver la hoja de datos (PDF) - ON Semiconductor
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Fabricante
MC100EP131FAR2G
ON Semiconductor
MC100EP131FAR2G Datasheet PDF : 11 Pages
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MC10EP131, MC100EP131
Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0
D2 SET R3 D3 VEE C3 C3 VCC
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
R2 1
VCC
25
16
VCC
C2 2
24 Q3
23 Q3
C3
26
15
R0
C2 3
22 Q2
C3
27
14
D0
CC 4
VEE
28
13
VCC
CC 5
32−Lead LQFP Pinout
D3
29
(Top View)
12
C0
C1 6
MC10EP131
MC100EP131
21 Q2
20 Q1
19 Q1
R3
30
11
C0
C1 7
18 Q0
SET
31
10
R1
D1 8
17 Q0
D2
32
9
VEE
12345678
9 10 11 12 13 14 15 16
VEE R1 C0 C0 VCC D0 R0 VCC
Figure 2. 32−Lead QFN Pinout (Top View)
R2 C2 C2 CC CC C1 C1 D1
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
D3
Figure 1. 32−Lead LQFP Pinout (Top View)
C3
C3
Table 1. PIN DESCRIPTION
R3
PIN
FUNCTION
D0−3*
ECL Data Inputs
D2
C0−3*, C0−3* ECL Separate Clock Inputs
CC*, CC*
ECL Common Clock Inputs
C2
C2
R0−3*
ECL Asynchronous Reset
SET*
ECL Asynchronous Set
R2
Q0−3, Q0−3
VCC
VEE
EP for
QFN−32, only
ECL Data Outputs
Positive Supply
Negative Supply
The Exposed Pad (EP) on the
QFN−32 package bottom is
thermally connected to the die
for improved heat transfer out
of package. The exposed pad
must be attached to a heat−
sinking conduit. The pad is
electrically connected to VEE.
SET
CC
CC
R1
C1
C1
D1
* Pins will default LOW when left open.
S
D
Q
Q3
Q
Q3
R
S
D
Q
Q2
Q
Q2
R
R
Q
Q1
D SQ
Q1
Table 2. TRUTH TABLE
D
S*
R*
CLK
L
L
L
Z
H
L
L
Z
X
H
L
X
X
L
H
X
X
H
H
X
Z = LOW to HIGH Transition
* Pins will default low when left open.
Q
L
H
H
L
Undef
R0
C0
C0
D0
VEE
R
Q
Q0
D SQ
Q0
Figure 3. Logic Diagram
http://onsemi.com
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