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MC14042BFR1 Datasheet PDF : 8 Pages
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MC14042B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic
Symbol
VDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time, D to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 135 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.66 ns/pF) CL + 57 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.5 ns/pF) CL + 35 ns
tPLH,
tPHL
5.0
10
15
Propagation Delay Time, Clock to Q, Q
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (1.7 ns/pF) CL + 135 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.66 ns/pF) CL + 57 ns
tPLH, tPHL = (0.5 ns/pF) CL + 35 ns
tPLH,
tPHL
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Width
tWH
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Rise and Fall Time
tTLH,
tTHL
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Hold Time
th
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Setup Time
tsu
5.0
10
15
Min
Typ (8.)
Max
Unit
ns
—
100
200
—
50
100
—
40
80
no
—
220
440
—
90
180
—
60
120
ns
—
220
440
—
90
180
—
60
120
300
150
100
50
80
40
ns
—
—
—
µs
—
—
15
—
—
5.0
—
—
4.0
100
50
50
25
40
20
ns
—
—
—
ns
50
0
—
30
0
—
25
0
—
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
16
PULSE
GENERATOR 1
5
CLOCK Q0
2
6 POLARITY Q0
3
4
Q1
10
D0
Q1
9
7
D1
Q2
11
13
D2
14
Q2
12
Q3
1
D3
Q3
15
For Power Dissipation test, each output
is loaded with capacitance CL.
8 VSS
20 ns
DATA INPUT
tPLH
Q OUTPUT
10%
Q OUTPUT 90%
1
f
90%
50%
90%
20 ns
10%
tPHL
50%
tTLH
tTHL
tPHL
10%
50%
tTHL
tTLH
Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram
(Data to Output)
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