MC33596FJE/R2(2007) Ver la hoja de datos (PDF) - Freescale Semiconductor

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Fabricante

MC33596FJE/R2
(Rev.:2007)

PLL Tuned UHF Receiver for Data Transfer Applications

Freescale Semiconductor 

Configuration, Command, and Status Registers

A first SPI access allows RAGC to be set; a second SPI access is required to reset it.

FAGC (Freeze Automatic Gain Control) freezes both receiver AGC levels.

0 = No action

1 = Holds the gain at its current value

16.3 Frequency Register

Figure 22 defines the Frequency register, F.

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit Name

—

—

—

—

F11

F10

F9

Reset Value

0

1

0

0

1

0

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit Name

F7

F6

F5

F4

F3

F2

F1

Reset Value

0

0

0

0

0

0

0

Figure 22. F Register

Bit 8

F8

0

Bit 0

F0

0

Addr

$04

$05

How this register is used is determined by the FRM bit, which is described below.

FRM = 0 (User Friendly Access)

Bits F[11:0] define the carrier frequency Fcarrier. The local oscillator frequency FLO is then set

automatically to Fcarrier + FIF (with FIF = intermediate frequency).

FRM = 1 (Direct Access)

F[11:0] defines the receiver local oscillator frequency FLO

Table 15 defines the value to be binary coded in the frequency registers F[11;0], versus the desired

frequency value F (in Hz).

Table 15. Frequency Register Value versus Frequency Value F

CF[1:0]

00, 01

11

Frequency Register Value

(2 x F/Fref-35) x 2048

(F/Fref-35) x 2048

Conversely, Table 16 gives the desired frequency F and the frequency resolution versus the value of the

frequency registers F[11;0].

Table 16. Frequency Value F versus Frequency Register Value

CF[1:0]

00, 01

11

Frequency (Hz)

(35 + F[11;0]/2048)xFref/2

(35 + F[11;0]/2048)xFref

Frequency Resolution (Hz)

Fref/4096

Fref/2048

MC33596 Data Sheet, Rev. 3

Freescale Semiconductor

31

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