Timing Interval
Peripheral Device Write Timing
Address valid to ~WriteEnable low
Data setup time before ~WriteEnable high
Tn
T34-48
T36-49
Minimum
54 nsec
58 nsec
Maximum
Device Ready/ Outputs Initialized
T57
1 msec
Note 1 Performance figures and timing information valid at Fclk = 40.0 MHz only. For timing
information and performance parameters at Fclk < 40.0 MHz, contact PMD.
Note 2 For 8/16 interface modes only.
Note 3 The clock low/high split has an allowable range of 40-60%.
MC55000 Electrical Specification – Preliminary 11/14/2003
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