MPC5644A Ver la hoja de datos (PDF) - Freescale Semiconductor

Número de pieza

componentes Descripción

Fabricante

MPC5644A

Microcontroller

Freescale Semiconductor 

1.4.3 eDMA

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data

movements via 64 programmable channels, with minimal intervention from the host processor. The hardware

micro-architecture includes a DMA engine which performs source and destination address calculations, and the actual data

movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels.

This implementation is utilized to minimize the overall block size. The eDMA module provides the following features:

• All data movement via dual-address transfers: read from source, write to destination

• Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes

• Transfer control descriptor organized to support two-deep, nested transfer operations

• An inner data transfer loop defined by a “minor” byte transfer count

• An outer data transfer loop defined by a “major” iteration count

• Channel activation via one of three methods:

— Explicit software initiation

— Initiation via a channel-to-channel linking mechanism for continuous transfers

— Peripheral-paced hardware requests (one per channel)

• Support for fixed-priority and round-robin channel arbitration

• Channel completion reported via optional interrupt requests

• One interrupt per channel, optionally asserted at completion of major iteration count

• Error termination interrupts optionally enabled

• Support for scatter/gather DMA processing

• Ability to suspend channel transfers by a higher priority channel

1.4.4 Interrupt controller

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically

scheduled hard real-time systems.

For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor

is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt

request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that

lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of

interrupt request, the priority of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority

ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that

all tasks which share the resource cannot preempt each other.

The INTC provides the following features:

• 9-bit vector addresses

• Unique vector for each interrupt request source

• Hardware connection to processor or read from register

• Each interrupt source can assigned a specific priority by software

• Preemptive prioritized interrupt requests to processor

• ISR at a higher priority preempts executing ISRs or tasks at lower priorities

• Automatic pushing or popping of preempted priority to or from a LIFO

• Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources

• Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor

This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.

MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

7

Share Link: