MT48LC16M8A2TG-7ELIT Ver la hoja de datos (PDF) - Micron Technology
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MT48LC16M8A2TG-7ELIT Datasheet PDF : 59 Pages
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128Mb: x4, x8, x16
SDRAM
ALTERNATING BANK WRITE ACCESSES 1
T0
CLK
T1
T2
T3
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
WRITE
NOP
DQM /
DQML, DQMH
A0-A9, A11
tAS tAH
ROW
tCMS tCMH
COLUMN m2
T4
T5
T6
T7
ACTIVE
NOP
WRITE
NOP
ROW
COLUMN b 2
T8
T9
NOP
ACTIVE
ROW
A10
BA0, BA1
DQ
tAS tAH
ROW
ENABLE AUTO PRECHARGE
tAS tAH
BANK 0
BANK 0
tDS tDH tDS tDH
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD
DIN m
DIN m + 1
ROW
ENABLE AUTO PRECHARGE
BANK 1
tDS tDH
DIN m + 2
BANK 1
tDS tDH
tDS tDH
DIN m + 3
DIN b
tWR - BANK 0
tDS tDH tDS tDH
DIN b + 1
DIN b + 2
tRP - BANK 0
tRCD - BANK 1
ROW
BANK 0
tDS tDH
DIN b + 3
tRCD - BANK 0
tWR - BANK 1
DON’T CARE
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCKH
tCKS
tCMH
tCMS
-7E
MIN MAX
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
1.5
-75
MIN MAX
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
1.5
-8E
MIN MAX
1
2
3
3
8
10
1
2
1
2
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
-7E
-75
-8E
SYMBOL* MIN MAX MIN MAX MIN MAX UNITS
tDH
0.8
0.8
1
ns
tDS
1.5
1.5
2
ns
tRAS
37 120,000 44 120,000 50 120,000 ns
tRC
60
66
70
ns
tRCD
15
20
20
ns
tRP
15
20
20
ns
tRRD
14
15
20
ns
tWR
1 CLK +
1 CLK +
1 CLK +
–
7ns
7.5ns
7ns
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
53
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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