NB100LVEP91
Driver
Device
Q
Q
50 W
50 W
D
Receiver
Device
D
V TT
V TT = V CC - 2.0 V
Figure 11. Typical Termination for Output Driver and Device
Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
- ECLinPS Circuit Performance at Non-Standard VIH Levels
- ECL Clock Distribution Techniques
AN1503
- ECLinPS I/O SPICE Modeling Kit
AN1504
- Metastability and the ECLinPS Family
AN1560
- Low Voltage ECLinPS SPICE Modeling Kit
AN1650
- Using Wire-OR Ties in ECLinPS Designs
AN1672
- The ECL Translator Guide
AND8002
- Marking and Date Codes
AND8020
- Termination of ECL Logic Devices
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