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NCV70522
(Rev.:2009)

Micro-Stepping Motor Driver

ON Semiconductor 

AMIS−30522, NCV70522

Examples of Combined READ and WRITE Operations

In the following examples successive READ and WRITE

operations are combined. In Figure 21 the Master first reads

the status from Register at ADDR4 and at ADDR5 followed

by writing a control byte in Control Register at ADDR2.

Note that during the write command (in Figures 20 and 21)

the old data of the pointed register is returned at the moment

the new data is shifted in.

Registers are updated with the internal status at the rising

edge of the internal 522 clock when CS = 1

The NEW DATA is written into the corresponding

internal register at the rising edge of CS

CS

DI

DATA from previous

command or NOT VALID

after POR or RESET

DO

COMMAND

READ DATA

from ADDR4

DATA

OLD DATA

or NOT VALID

COMMAND

READ DATA

from ADDR5

DATA

DATA

from ADDR4

COMMAND

WRITE DATA

to ADDR2

DATA

DATA

from ADDR5

DATA

NEW DATA

for ADDR2

DATA

OLD DATA

from ADDR2

Figure 21. Two Successive READ Commands Followed by a WRITE Command

After the write operation the Master could initiate a read

back command in order to verify if the data is correctly

written, as illustrated in Figure 22. During reception of the

READ command the old data is returned for a second time.

Only after receiving the READ command the new data is

transmitted. This rule also applies when the master device

wants to initiate an SPI transfer to read the Status Registers.

Because the internal system clock updates the Status

Registers only when CS line is high, the first read out byte

might represent old status information.

Registers are Updated with the Internal

Status at the Rising Edge of CS

CS

Registers are Updated with the In-

ternal Status at the Rising Edge of

the Internal 522 Clock when CS = 1

DI

DATA from previous

command or NOT VALID

after POR or RESET

DO

COMMAND

WRITE DATA

to ADDR2

DATA

OLD DATA

or NOT VALID

DATA

NEW DATA

for ADDR2

DATA

OLD DATA

from ADDR2

COMMAND

READ DATA

from ADDR2

DATA

OLD DATA

from ADDR2

COMMAND or

DUMMY

DATA

NEW DATA

from ADDR2

Figure 22. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2 Followed by

a READ Back Operation to Verify a Correct WRITE Operation

NOTE: The internal data−out shift buffer of the AMIS−30522/NCV70522 is updated with the content of the selected SPI register only at the

last (every eighth) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission

cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.

Table 11. SPI CONTROL REGISTERS

(All SPI Control Registers have Read/Write Access and default to “0” after Power−on or hard reset)

Structure

Content

Bit 7

Bit 6 Bit 5 Bit 4

Bit 3

Bit 2

Access

R/W

R/W R/W R/W

R/W

R/W

Address

Reset

0

0

0

0

0

0

CRWD (00h)

Data

WDEN

WDT[3:0]

0

CR0 (01h)

Data

SM[2:0]

CUR[4:0]

CR1 (02h)

Data

DIRCTRL NXTP

−

−

PWMF PWMJ

CR2 (03h)

Data

MOTEN

SLP SLAG SLAT

−

−

Bit 1

R/W

0

0

Bit 0

R/W

0

0

EMC[1:0]

−

−

Where:

R/W:

Reset:

WDEN:

WDT[3:0]:

Read and Write access

Status after Power−On or hard reset

Watchdog enable. Writing “0” to this bit will clear WD bit (see SPI Status Register 0)

Watchdog timeout interval

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