NT7701
Segment Mode 2 (VSS = V5 = 0V, VDD = 2.5 - 4.5V, V0 = 15 to 30, and TA = -30 to +85°C, unless otherwise noted)
Parameter
Shift clock period
Symbol
tWCK
Min.
125
Typ.
-
Max. Unit
ns
Condition
tr, tf ≦ 11ns, Note 1
Shift clock "H" pulse width
tWCKH
51
-
ns
Shift clock "L" pulse width
tWCKL
51
-
ns
Data setup time
tDS
30
-
ns
Data hole time
tDH
40
-
ns
Latch pulse "H" pulse width
tWLPH
51
-
ns
Shift clock rise to Latch pulse rise time
tLD
0
-
ns
Shift clock fall to Latch pulse fall time
tSL
51
-
ns
Latch pulse rise to Shift clock rise time
tLS
51
-
ns
Latch pulse fall to Shift clock fall time
tLH
51
-
ns
Input signal rise time
tr
-
50
ns Note 2
Input signal fall time
tf
-
50
ns Note 2
Enable setup time
tS
36
-
ns
DISPOFF Removal time
tSD
100
-
ns
DISPOFF enable pulse width
Output delay time (1)
Output delay time (2)
Output delay time (3)
tWDL
1.2
-
µs
tD
tpd1, tpd2
-
78
ns CL = 15pF
-
1.2
µs CL = 15pF
tpd3
-
1.2
µs CL = 15pF
Note
1. Take the cascade connection into consideration.
2. (tCK - tWCKII - tWCKL)/2 is the maximum in the case of high speed operation.
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