AD8307ANZ1 Ver la hoja de datos (PDF) - Analog Devices

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AD8307ANZ1

Low Cost, DC to 500 MHz, 92 dB Logarithmic Amplifier

Analog Devices 

Data Sheet

AD8307

SPECIFICATIONS

VS = 5 V, TA = 25°C, RL ≥ 1 MΩ, unless otherwise noted.

Table 2.

Parameter

GENERAL CHARACTERISTICS

Input Range (±3 dB Error)

Input Range (±1 dB Error)

Logarithmic Conformance

Logarithmic Slope

vs. Temperature

Logarithmic Intercept

vs. Temperature

Input Noise Spectral Density

Operating Noise Floor

Output Resistance

Internal Load Capacitance

Response Time

Upper Usable Frequency

Lower Usable Frequency

AMPLIFIER CELL CHARACTERISTICS

Cell Bandwidth

Cell Gain

INPUT CHARACTERISTICS

DC Common-Mode Voltage

Common-Mode Range

DC Input Offset Voltage3

Incremental Input Resistance

Input Capacitance

Bias Current

POWER INTERFACES

Supply Voltage

Supply Current

Disabled

Conditions

From noise floor to maximum input

From noise floor to maximum input

f ≤ 100 MHz, central 80 dB

f = 500 MHz, central 75 dB

Unadjusted1

Sine amplitude, unadjusted2

Equivalent sine power in 50 Ω

Inputs shorted

RSOURCE = 50 Ω/2

Pin 4 to ground

Small signal, 10% to 90%, 0 mV to 100 mV, CL = 2 pF

Large signal, 10% to 90%, 0 V to 2.4 V, CL = 2 pF

AC-coupled input

−3 dB

AC-coupled input

Either input (small signal)

RSOURCE ≤ 50 Ω

Drift

Differential

Either pin to ground

Either input

VENB ≥ 2 V

VENB ≤ 1 V

Min Typ Max Unit

92

88

±0.3 ±1

±0.5

23 25 27

23

27

20

−87 −84 −77

−88

−76

1.5

−78

10 12.5 15

3.5

400

500

500

10

dB

dB

dB

dB

mV/dB

mV/dB

μV

dBm

dBm

nV/√Hz

dBm

kΩ

pF

ns

ns

MHz

Hz

900

MHz

14.3

dB

3.2

V

−0.3 +1.6 VS − 1 V

50 500 μV

0.8

μV/°C

1.1

kΩ

1.4

pF

10 25

μA

2.7

5.5

V

8

10

mA

150 750 μA

1 This can be adjusted downward by adding a shunt resistor from the output to ground. A 50 kΩ resistor reduces the nominal slope to 20 mV/dB.

2 This can be adjusted in either direction by a voltage applied to Pin 5, with a scale factor of 8 dB/V.

3 Normally nulled automatically by internal offset correction loop and can be manually nulled by a voltage applied between Pin 3 and ground; see the Applications

Information section.

Rev. E | Page 3 of 24

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