KM4112 Ver la hoja de datos (PDF) - Fairchild Semiconductor
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KM4112 Datasheet PDF : 9 Pages
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KM4112
DATA SHEET
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. Fairchild has evaluation
boards to use as a guide for high frequency layout
and to aid in device testing and characterization.
Follow the steps below as a basis for high frequency
layout:
I Include 6.8µF and 0.01µF ceramic capacitors
I Place the 6.8µF capacitor within 0.75 inches
of the power pin
I Place the 0.01µF capacitor within 0.1 inches
of the power pin
I Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance
I Minimize all trace lengths to reduce
series inductances
Refer to the evaluation board layouts shown in Figure
6 for more information.
Evaluation Board Information
The following evaluation boards are available to aid
in the testing and layout of this device:
The KEB002 evaluation board is built for dual supply
operation. Follow these steps to use the board in a
single supply application:
1. Short -Vs to ground
2. Use C3 and C4, if the -Vs pin of the KM4112 is not
directly connected to the ground plane.
Eval Board
KEB002
Description
Products
Single Channel,
KM4112IT5
Dual Supply 5 & 6 lead SOT23
Evaluation board schematics and layouts are shown in
Figure 5 and Figure 6.
Figure 5: Evaluation Board Schematic
REV. 2 July 2001
7
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