tm TE
CH
T431616A
DC CHARACTERISTICS
TA = -5 to 70°C / -40 to +85 °C , VIH(min)/VIL(max)=2.0V/0.8V
Speed version
Parameter Symbol
Unit
Test Condition
Note
-6 -7 -8 -10
Operating Current
ICC1
( One Bank Active)
Burst Length = 1
160 150 140 120 mA
1,3
tRC≥tRC(min) ,tCC≥tCC(min),IOL= 0 mA
Precharge Standby ICC2P
Current in power-
down mode
ICC2PS
2
CKE ≤ VIL(max),tCC=15ns
mA
3
2
CKE ≤ VIL(max),CLK ≤ VIL(max), tCC =•
Precharge Standby
CKE ≥ VIH(min), CS ≥ VIH(min),tCC=15ns
ICC2N
30
Current in non
power-down mode
Input signals are changed one time during 30ns
mA
3
CKE≥VIH(min),CLK ≤ VIL(min),tCC=•
ICC2NS
2
Input signals are stable
Active Standby ICC3P
Current in power-
down mode
ICC3PS
10
CKE ≤ VIL(max),tCC=15ns
mA
3
10
CKE ≤ VIL(max),CLK ≤ VIL(max),tCC=•
Active Standby
CKE≥VIH(min), CS ≥VIH(min),tCC=15ns
Current in non
ICC3N
40
Input signals are changed one time during 30ns
power-down mode
mA
3
CKE≥VIH(min),CLK ≤ VIL(min),tCC=•
(One Bank Active) ICC3NS
10
Input signals are stable
Operating Current
(Burst Mode)
ICC4
180 170 160 140
CAS Latency 3 IOL=0 mA,Page Burst
mA
All Band Activated
1,3
180 170 160 140
CAS Latency 2
tCCD= tCCD(min)
Refresh Current ICC5
180 170 160 140 mA tRC ≥tRC(min)
2,3
Self refresh
Current
ICC6
1
mA CKE ≤ 0.2V
Note:
1. Measured with output open. Addresses are changed only one time during tCC(min) .
2. Refresh period is 32ms. Addresses are changed only one time during tCC(min) .
3. tCC : Clock cycle time.
tRC : Row cycle time.
tCCD : Column address to column address delay time.
Taiwan Memory Technology, Inc. reserves the right P. 6
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C