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ADV7202 Datasheet PDF : 28 Pages
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ADV7202
FUNCTIONAL DESCRIPTION
Analog Inputs
The ADV7202 has the capability of sampling up to five CVBS
video input signals, two component YUV, or three S-Video
inputs. Eight auxiliary general-purpose inputs are also available.
Table I shows the analog signal input options available and pro-
grammable by I2C. When configured for auxiliary input mode,
the CVBS inputs are single-ended with the second differential
input internally set to VREFADC. The resolution on the front
end digitizer is 12 bits; 2 bits (12 dB) are used for gain and offset
adjustment. The digitizer has a conversion rate of up to 54 MHz.
The eight auxiliary inputs can be used for system monitoring, etc.
and are sampled by an 843 kHz* SAR ADC. The analog input
signal range will be dependent on the value of VREFADC and
the SHA gain see (Table II). Three on-screen display inputs
OSDIN[2:0] mux to the DAC outputs to enable support for
Picture-on-Picture applications.
Table I. Analog Input Signal Data
Register
Setting Description
SHA
Used Sync_Out
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
CVBS in on AIN1
0
Figure 1
CVBS in on AIN2
0
Figure 1
CVBS in on AIN3
1
Figure 1
Reserved
1
CVBS in on AIN5
0
Figure 1
CVBS in on AIN6
2
Figure 1
Y/C, Y on AIN1, C on AIN4 0, 1 Figure 2
Y/C, Y on AIN2, C on AIN3 0, 1 Figure 2
YUV, Y on AIN2, U on AIN3, 0, 1, 2 Figure 3
V on AIN6
CVBS on AIN1 and 8 AUX. 0
Figure 1
I/Ps AIN3–AIN6*.
CVBS on AIN2 and 8 AUX. 0
Figure 1
I/Ps AIN3–AIN6*.
*AUX inputs are single-ended. All other inputs are differential.
Table II. Analog Input Signal Range
I/P Mode VREFOUT (V)
Differential 2.2
Differential 2.2
Differential 1.1
Differential 1.1
Single-Ended 2.2
Single-Ended 2.2
Single-Ended 1.1
Single-Ended 1.1
SHA
Gain
1
2
1
2
1
2
1
2
Input Range (V)
Min
Max
–2.2
–1.1
–1.1
–0.55
0
1.1
0
0.55
+2.2
+1.1
+1.1
+0.55
4.4
3.3
2.2
1.65
Digital Inputs
The DAC digital inputs on the ADV7202 [9:0] are TTL
compatible. Data may be latched into the device in three different
modes, programmable via I2C.
DAC Mode 1, single clock, single edge (see Figure 10) uses only
the rising edge of DACCLK1 to latch data into the device.
DACCLK0 is a data line that goes high to indicate that the data
is for DAC0. Subsequent data-words go to the next DAC in
sequence.
DAC Mode 2, dual edge, dual clock (see Figure 11) clocks data
in on both edges of DACCLK0 and DACCLK1. Using this
option, data can be latched into the device at four times the
clock speed. All four DACs are used in this mode.
DAC Mode 3, 4:2:2 mode (see Figure 12). Using this option,
4:2:2 video data is latched in using DACCLK1, while DACCLK0
is used as a data line that is brought to a high state when Cr data
is input; hence Y will appear on DAC1, Cr on DAC2, and Cb
on DAC0.
Analog Outputs
Analog outputs [DAC0–DAC3] consist of four 10-bit DACs that
run at up to 54 MHz or up to 200 MHz if only DAC0 is used.
These outputs can be used to output CVBS, S-Video, Compo-
nent YCrCb, and RGB.
Digital Outputs
Video data will be clocked out on DOUT[9:0] on the rising edge
of XTAL0 (see Figure 13). Auxiliary data can be read out via
I2C compatible MPU port.
I2C Control
I2C operation allows both reading and writing of system registers.
Its operation is explained in detail in the MPU Port Descrip-
tion section.
*Fclk/32, 843 kHz for nominal 27 MHz
–10–
REV. 0
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