Philips Semiconductors
Pager baseband controller
Product specification
PCA5010
handbook, full pagewidth
P2
dummy fetch cycles, will be discarded
00 00 00 00 30 30 30 30 30
P0
02 30 00 XX 75 87 01 XX
ALE
PSEN
EA
RESOUT
RESETIN
minimum 259 clocks
on XTL1
(f < 100 kHz)
See Fig.8.
ALE, PSEN latched
clocking on TCLK(1)
(f = 500 kHz)
mode entry
Fig.70 Program mode entry.
microcontroller idle
parallel programming mode
MGR166
handbook, full pagewidth
VPP
P0.7 to P0.0
P2.1/LS0
P2.0/LS1
P2.2/PGM
P2.3/RdStrb
P2.5/WEB
1998 Nov 02
set verify
check
mode
security
VDD = 12.5 to 13 V
01H
XX
initialization ready
Fig.71 Parallel program mode initialization.
101
MGR167