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PCA9545PW

4-channel I2C switch with interrupt logic and reset

Philips Electronics 

Philips Semiconductors

4-channel I2C switch with interrupt logic and reset

Product data

PCA9545

DEVICE ADDRESS

Following a START condition the bus master must output the

address of the slave it is accessing. The address of the PCA9545 is

shown in Figure 3. To conserve power, no internal pullup resistors

are incorporated on the hardware selectable address pins and they

must be pulled HIGH or LOW.

1 1 1 0 0 A1 A0 R/W

FIXED

HARDWARE SELECTABLE

SW00893

Figure 3. Slave address

The last bit of the slave address defines the operation to be

performed. When set to logic 1, a read is selected while a logic 0

selects a write operation.

CONTROL REGISTER

Following the successful acknowledgement of the slave address,

the bus master will send a byte to the PCA9545, which will be stored

in the control register. If multiple bytes are received by the

PCA9545, it will save the last byte received. This register can be

written and read via the I2C bus.

INTERRUPT BITS CHANNEL SELECTION BITS

(READ ONLY)

(READ/WRITE)

7 65 4 3 21 0

INT3 INT2 INT1 INT0 B3 B2 B1 B0

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

INT0

INT1

INT2

INT3 SW00949

Figure 4. Control Register

CONTROL REGISTER DEFINITION

One or several SCx/SDx downstream pair, or channel, is selected

by the contents of the control register. This register is written after

the PCA9545 has been addressed. The 2 LSBs of the control byte

are used to determine which channel is to be selected. When a

channel is selected, the channel will become active after a stop

condition has been placed on the I2C bus. This ensures that all

SCx/SDx lines will be in a HIGH state when the channel is made

active, so that no false conditions are generated at the time of

connection.

Table 1. Control Register; Write — Channel Selection/

Read — Channel Status

INT3 INT2 INT1 INT0 B3 B2 B1 B0 COMMAND

0

Channel 0

disabled

X

X

X

X

X

X

X

1

Channel 0

enabled

0

Channel 1

disabled

X

X

X

X

X

X

X

1

Channel 1

enabled

0

Channel 2

disabled

X

X

X

X

X

X

X

1

Channel 2

enabled

0

Channel 3

disabled

X

X

X

X

1

X

X

X Channel 3

enabled

NOTE: Several channels can be enabled at the same time.

Ex: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and 3 are

disabled and channel 1 and 2 are enabled.

Care should be taken not to exceed the maximum bus capacity.

2002 Mar 28

4

853-2302 27311

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