PSD813F1-A Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

PSD813F1-A

Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs

STMicroelectronics 

Preliminary

2.0

Key Features

PSD813F1-A

t A simple interface to 8-bit microcontrollers that use either multiplexed or

non-multiplexed busses. The bus interface logic uses the control signals generated by

the microcontroller automatically when the address is decoded and a read or write is

performed. A partial list of the MCU families supported include:

• Intel 8031, 80196, 80186, 80C251, and 80386EX

• Motorola 68HC11, 68HC16, 68HC12, and 683XX

• Philips 8031 and 8051XA

• Zilog Z80 and Z8

t Internal 1 Mbit Flash memory. This is the main Flash memory. It is divided into eight

equal-sized blocks that can be accessed with user-specified addresses.

t Internal secondary 256 Kbit EEPROM memory. It is divided into four equal-sized blocks

that can be accessed with user-specified addresses. This secondary memory brings

the ability to execute code and update the main Flash concurrently.

t 16 Kbit scratchpad SRAM. The SRAM’s contents can be protected from a power failure

by connecting an external battery.

t Optional 64 byte One Time Programmable (OTP) memory that can be used for product

configuration and calibration.

t CPLD with 16 Output Micro⇔Cells (OMCs) and 24 Input Micro⇔Cells (IMCs). The

CPLD may be used to efficiently implement a variety of logic functions for internal

and external control. Examples include state machines, loadable shift registers, and

loadable counters.

t Decode PLD (DPLD) that decodes address for selection of internal memory blocks.

The DPLD can also be used to generate external chip selects.

t 27 individually configurable I/O port pins that can be used for the following functions:

• MCU I/Os

• PLD I/Os

• Latched MCU address output

• Special function I/Os.

• 16 of the I/O ports may be configured as open-drain outputs.

t Standby current as low as 50 µA for 5 V devices, 25 µA for 3 V devices.

t Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).

With it, you can program a blank device or reprogram a device in the factory or the field.

t Internal page register that can be used to expand the microcontroller address space by

a factor of 256.

t Internal programmable Power Management Unit (PMU) that supports a low power mode

called Power Down Mode. The PMU can automatically detect a lack of microcontroller

activity and put the PSD813F1 into Power Down Mode.

t Erase/Write cycles:

• Flash memory – 100,000 minimum

• EEPROM – 10,000 minimum

• PLD – 1,000 minimum

• Data Retention: 15 year minimum at 90 degrees Celsius (for Main Flash, Boot, PLD

and Configuration bits).

3

Share Link: