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SAA4956TJ

2.9-Mbit field memory with noise reduction

Philips Electronics 

Philips Semiconductors

2.9-Mbit field memory with noise reduction

Preliminary specification

SAA4956TJ

7.2 Noise reduction function

handbook, full pagewidth

I2C-bus control:

chroma_inverted

DPCMin

data input

D0(V0), D1(V1)

D2(U0), D3(U1)

4

REFORMATTER

new U/V

−

delta U/V

LOW-PASS

FILTER 1

I2C-bus control:

unfiltered

LF delta U/V

D-field delay

D0(V0), D1(V1)

D2(U0), D3(U1)

4

REFORMATTER

old U/V

data input

D11(Y7) to D4(Y0)

8

new Y

−

delta Y

−+

LOW-PASS

FILTER 1

I2C-bus control:

unfiltered

LF delta Y

D-field delay

D11(Y7) to D4(Y0)

8

old Y

−+

ABS/LIMITER

U/V

AVERAGE

HF

delta

U/V

ABS/LIMITER

HF

delta

Y

LOW-PASS

FILTER 2

I2C-bus control:

Cadapt_gain

×

I2C-bus control:

chromafix and

Klumatochroma

Kchroma

Kchromafix

×

Kluma

LUT

+

LOW-PASS

FILTER 2

I2C-bus control:

Yadapt_gain

×

I2C-bus control:

lumafix

Klumafix

Kluma

×

LUT

+

Switch position is off.

I2C-bus control:

noise_shape

+

processed U/V

NOISE SHAPE

I2C-bus control:

DPCMout

FORMATTER

4

D to memory

D0(V0), D1(V1)

D2(U0), D3(U1)

I2C-bus control:

noise_shape

+

processed Y

NOISE SHAPE

8

D to memory

D11(Y7) to D4(Y0)

MGR689

Fig.3 Block diagram of noise reduction.

1998 Dec 08

11

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