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SC18IS602B Datasheet PDF : 25 Pages
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NXP Semiconductors
SC18IS602/602B/603
I2C-bus to SPI bridge
7. Functional description
The SC18IS602/602B/603 acts as a bridge between an I2C-bus and an SPI interface. It
allows an I2C-bus master device to communicate with any SPI-enabled device.
7.1 I2C-bus interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves
• Multi-master bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
• The I2C-bus may be used for test and diagnostic purposes
A typical I2C-bus conï¬guration is shown in Figure 4. (Refer to NXP Semiconductors’
UM10204, “I2C-bus speciï¬cation and user manualâ€, document order number
9398 393 40011.)
VDD
RPU
RPU
I2C-bus
SDA
SCL
SC18IS602/602B/603
I2C-BUS
DEVICE
I2C-BUS
DEVICE
002aac445
Fig 4. I2C-bus conï¬guration
The SC18IS602/602B/603 device provides a byte-oriented I2C-bus interface that supports
data transfers up to 400 kHz. When the I2C-bus master is reading data from SC18IS60x,
the device will be a slave-transmitter. The SC18IS60x will be a slave-receiver when the
I2C-bus master is sending data. At no time does the SC18IS60x act as an I2C-bus master,
however, it does have the ability to hold the SCL line LOW between bytes to complete its
internal processes.
SC18IS602_602B_603_4
Product data sheet
Rev. 04 — 11 March 2008
© NXP B.V. 2008. All rights reserved.
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