Si3035
Table 8. Switching Characteristics—Serial Interface (DCE = 0)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Cycle time, SCLK
tc
354
1/256 Fs
—
ns
SCLK duty cycle
tdty
—
50
—
%
Delay time, SCLK ↑ to FSYNC ↓
td1
—
—
10
ns
Delay time, SCLK ↑ to SDO valid
td2
—
—
20
ns
Delay time, SCLK ↑ to FSYNC ↑
td3
—
—
10
ns
Setup time, SDI before SCLK ↓
tsu
25
—
—
ns
Hold time, SDI after SCLK ↓
th
20
—
—
ns
Setup time, FC ↑ before SCLK ↑
tsfc
40
—
—
ns
Hold time, FC ↑ after SCLK ↑
thfc
40
—
—
ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V
SCLK
FSYNC
(mode 0)
FSYNC
(mode 1)
16 Bit
SDO
16 Bit
SDI
FC
tc
td1
VOH
VOL
td3
td3
td2
D15
D14
tsu
th
D15
D14
D1
D0
D1
D0
tsfc
thfc
Figure 3. Serial Interface Timing Diagram
8
Rev. 1.2