SM5844 Ver la hoja de datos (PDF) - Nippon Precision Circuits
Número de pieza
componentes Descripción
Fabricante
SM5844 Datasheet PDF : 26 Pages
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SM5844AF
PIN DESCRIPTION
Number1
1, 2
3, 4
5
6
7
8, 9
Name
DI
BCKI
LRCI3
ICLK
ICKSL
IFM1
10, 11
IFM2
I/O2
Description
Ip
Data input
Ip
Input bit clock
Ip
Input word clock (fsi)
I
Input system clock input
Ip
Input system clock (ICLK) select. 384fsi when HIGH, and 256fsi when LOW .
Input format select
Ip
IFM1
IFM2
W ord length
Data sequence
Data position
LOW
LOW
LOW
HIGH
16 bits
MSB first
Rear packed
Ip
HIGH
LOW
20 bits
HIGH
HIGH
LSB first
Front packed
Rear packed
12, 13
14, 15
16
17
18
VDD
DMUTE
MCOM
MDT/FSI1
MCK/FSI2
–
5 V supply pin
Ip
Direct mute pin
Ip
Interface switch control pin. MDT, MCK and MLEN control when HIGH. FSI1, FSI2 and DEEM
control when LOW .
When MCOM is LOW: Deemphasis frequency
Ip
When MCOM is HIGH: Microcontroller interface set pins
data input (MDT)
FSI1
FSI2
fsi
LOW
HIGH
48.0 kHz
Ip
When MCOM is HIGH: Microcontroller interface
bit clock (MCK)
×
HIGH
LOW
HIGH
44.1 kHz
32.0 kHz
19, 20
MLEN/DEEM
21, 22
OW18N
23, 24
OW20N
Ip
When MCOM is HIGH: Microcontroller data word latch clock (MLEN)
When MCOM is LOW: Deemphasis ON/OFF control (DEEM)
Output format select
When IISN = HIGH (normal mode)
OW20N
OW18N
W ord length
Ip
LOW
LOW
LOW
HIGH
20 bits
HIGH
LOW
18 bits
HIGH
HIGH
16 bits
When IISN = LOW (IIS mode)
OW20N
OW18N
W ord length
LOW
Ip
LOW
LOW
HIGH
20 bits
HIGH
LOW
18 bits
HIGH
HIGH
16 bits
Data position
Front packed
Rear packed
Data position
IIS mode
Front packed
25, 26
27
28
29
IISN
S TAT E
TST1N
TST2N
Ip
IIS output mode select. Normal mode when HIGH, and IIS mode when LOW.
O
Internal operation status output (for operation check)
Ip
Output dither control. Dither ON when LOW , and OFF when HIGH.
Ip
Test pin. Test mode when LOW . Normal operating mode when HIGH.
NIPPON PRECISION CIRCUITS—4
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