ST70235A Ver la hoja de datos (PDF) - STMicroelectronics

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Fabricante

ST70235A

ASCOT™ DMT TRANSCEIVER

STMicroelectronics 

ST70235A

PIN SUMMARY

Mnemonic

Type

BS Type

Number

of Signals

Function

Power Supply

VDD 3.3

VDD 1.8

VSS

ATC INTERFACE

ALE

I

C

PCLK

I

I

CSB

I

I

BE1

I

I

WR_RDB

I

I

RDYB

OZ

O

INTB

O

O

AD

IO

B

OBC_TYPE

I-PD

I

TEST ACCESS PART INTERFACE

TDI

I-PU

TDO

OZ

TCK

I-PD

TMS

I-PU

TRSTB

I-PD

ANALOG FRONT END INTERFACE

AFRXD

I

I

AFTXD

O

O

CLWD

I

I

PDOWN

O

O

CTRLDATA

O

O

MCLK

I

C

ATM UTOPIA INTERFACE

U_RxData

OZ

B

U_TxData

I

I

U_RxADDR

I

I

U_TxADDR

I

I

U_RxCLAV

OZ

O

U_TxCLAV

OZ

O

U_RxENBB

I-TTL

I

U_TxENBB

I-TTL

I

U_RxSOC

OZ

O

U_TxSOC

I-TTL

I

U_RxCLK

I-TTL

C

U_TxCLK

I-TTL

C

U_RxRefB

O

O

U_TxRefB

I-TTL

I

(VSS + 3.3V) Power supply

(VSS + 1.8V) Power supply

0V Ground

1

Used to latch the address of the internal register to be accessed

1

Processor clock

1

Chip selected to respond to bus cycle

1

Address 1 (not multiplexed)

1

Specifies the direction of the access cycle

1

Controls the ATC bus cycle termination

1

Requests ATC interrupt service

16

Multiplexed Address/Data bus

1

Select between i960 (0) or generic (1) controller interface

1

Refer to section

1

1

1

1

4

Receive data nibble

4

Transmit data nibble

1

Start of word indication

1

Power down analog front end

1

Serial data transmit channel

1

Master cloc

8

Receive interface Data

8

Transmit interface Data

5

Receive interface Address

5

Transmit interface Address

1

Receive interface Cell Available

1

Transmit interface Cell Available

1

Receive interface Enable

1

Transmit interface Enable

1

Receive interface Start of Cell

1

Transmit interface Start of Cell

1

Receive interface Utopia Clock

1

Transmit interface Utopia Clock

1

8kHz reference clock to ATM device

1

8kHz reference clock from ATM device

8/28

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