SP8853/A/DG Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc
Número de pieza
componentes Descripción
Fabricante
SP8853/A/DG Datasheet PDF : 14 Pages
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SP8853
An F1 or F2 update cycle will consist of a byte containing
24 bits whereas the reference byte will contain 18 bits. The
device requires 3 bytes, each with a chip select sequence,
totalling 66 bits to fully program.
When the dual modulus A counter is set to 48/9, the data
required to set the counter is reduced by one bit, leaving an
Data Sheet
unused bit in the 22-bit F1/F2 buffer. This bit must always be
set to zero when the 48/9 mode is required. Various
programming sequences are shown in Fig. 7.
The data entry and storage registers are always powered
up, making it possible to enter data when the device is in the
powered down state.
PD2
0
1
0
1
PD2
0
0
1
1
Result
FREF and FPD outputs off, charge pumps 1 and 2 on
FREF and FPD outputs on, charge pump 1 off, charge pump 2 on
FREF and FPD outputs off, charge pump 1 disabled by lock detect, charge pump 2 on
FREF and FPD outputs on, charge pump 1 disabled by lock detect, charge pump 2 on
Table 4
LOOP FILTER 15V
15V FREF
FPD
C2
C1
Rx
R2
15V
2·2k
15V
SL562
Rx
VCC
2
VOLTAGE
1n
CONTROLLED
OSCILLATOR
0·1µ
1n
Fig. 6a Typical application
4 3 2 1 28 27 26
5
25
6
24
7
23
8
SP8853
22
9
21
10
20
11
19
12 13 14 15 16 17 18
0·25
Rb RPD Rb > PD2 current
15V
33p
39p
CONTROL
1n
MICRO
21 NC
20
19
EXTERNAL
REFERENCE
SOURCE
Fig. 6b Connection
of external reference
VCC
TO LOOP
AMPLIFIER
VCC
Cd
Ra
3 2 1 28 27 26
SP8853
25
24
Ra
0·25
Ra > 23
PD2 current
Fig. 6c Use of lock detect circuit with PD1
FROM
CHARGE
PUMP
VARICAP
15V
SUPPLY
10k
LOOP
470
FILTER
TO VCO
22k
Fig. 6d Simple discrete amplifier
Fig. 6 Application diagrams
6
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