ST7588T
n REVERSION HISTORY
Version
1.0
1.1
1.2
1.2a
1.3
Data
1.
2005/08/01
2.
1.
2.
2005/11/11
3.
4.
2005/12/22 1.
2005/12/29 1.
1.
2.
2007/09/20
3.
4.
5.
Description
Remove “Preliminary”.
Update I2C SCL clock frequency.
Chip thickness.
Redraw some figures.
Bias default value BS[2:0]=010.
Update VDD2 range.
Remove History before V1.0.
Add voltage endurance warning to Booster Connection.
Fix description mistake.
Remove Master-Slave related sections. Master-Slave function is reserved for special
specification by customer.
Redraw timing figures.
Remove I2C timing at 1.8V.
Fix Power Save flow mistake.
Ver 1.3
61/61
2007/09/20