SY89467U Ver la hoja de datos (PDF) - Micrel
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Fabricante
SY89467U Datasheet PDF : 15 Pages
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Micrel, Inc.
SY89467U
Pin Description
Pin Number
1, 16, 23, 33
41, 48, 58
64, 63
62, 61
60, 59
57, 56
55, 54
53, 52
51, 50
47, 46
45, 44
43, 42
39, 38
37, 36
35, 34
31, 30
29, 28
27, 26
25, 24
22, 21
20, 19
18, 17
4, 13
5, 12
6, 7
10, 11
2, 3, 14, 15,
32, 40, 49
9
8
Pin Name
VCC
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
Q9, /Q9
Q10, /Q10
Q11, /Q11
Q12, /Q12
Q13, /Q13
Q14, /Q14
Q15, /Q15
Q16, /Q16
Q17, /Q17
Q18, /Q18
Q19, /Q19
VREF-AC0
VREF-AC1
VT0, VT1
IN0, /IN0
IN1, /IN1
GND,
Exposed
Pad
OE
SEL
Pin Function
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close to the VCC
pins as possible.
LVPECL Differential Output Pairs: Differential buffered output copies of the selected input
signal. The output swing is typically 800mV. Unused output pairs may be left floating with no
impact on jitter. See “LVPECL Output Termination” subsection. Normally terminated with 50Ω
to VCC-2V. These differential LVPECL outputs are a logic function of the IN0, IN1, and SEL
inputs. See “Truth Table” below.
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling inputs IN
and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low
ESR capacitor to VCC. Due to limited drive capability, each VREF-AC pin is only intended to
drive its respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface
Applications” subsection.
Input Termination Center-Tap: Each side of a differential input pair terminates to the VT pin.
The VT pin provides a center-tap for each input (IN, /IN) to a termination network for
maximum interface flexibility. See “Input Interface Applications” subsection.
Differential Inputs: These input pairs are the differential signal inputs to the device. These
inputs accept AC- or DC-coupled signals as small as 100mV. The input pairs internally
terminate to a VT pin through 50Ω. This allows a wide input voltage range from VCC to
GND. See Figure 3a, Simplified Differential Input Stage for details. Note that when these
inputs are left in an open state, the FSI feature will override this input state and provide a
valid state at the output. See “Functional Description” subsection.
Ground. Exposed pad must be connected to a ground plane that is the same potential as the
ground pins.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q19 outputs. It is
internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left
open. When disabled, Q goes LOW and /Q goes HIGH. OE being synchronous, outputs will
be enabled/disabled following a rising and a falling edge of the input clock. VTH = VCC/2.
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will
default to logic HIGH state if left open. VTH = VCC/2.
Truth Table
Inputs
IN0 /IN0 IN1 /IN1 SEL
0
1
X
X
0
1
0
X
X
0
X
X
0
1
1
X
X
1
0
1
Outputs
Q
/Q
0
1
1
0
0
1
1
0
April 2008
3
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
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