TC7109/A
Integrator Output
for Over Range Input
Integrator
Saturates
Integrator Output
for Normal Input
Internal Clock
AZ
Phase I
INT
Phase II
Internal Latch
Status Output
2048
Counts
Min.
Fixed
2048
Counts
Number of Counts to Zero Crossing
Proportional to VIN
No Zero Crossing
Zero Crossing
Occurs
Zero Crossing
Detected
DE
Phase III
ZI
AZ
Zero Integrator
Phase forces
Integrator Output
to 0V
AZ
4096
Counts
Max
After Zero Crossing, Analog section will
be in Auto-Zero Configuration
FIGURE 3-1:
Conversion Timing (RUN/HOLD) Pin High
TEST
17
High Order
Low Order
Byte Outputs
Byte Outputs
BBBBBBBBBBBB
POL OR 12 11 10 9 8 7 6 5 4 3 2 1
3 4 5 6 7 8 9 10 11 12 13 14 15 16
14 Three-State Outputs
14 Latches
12-Bit Counter
Latch
Clock
To
Analog
Section
COMP OUT
AZ
INT
DE (±)
ZI
Conversion
Control Logic
Oscillator and
Clock Circuitry
Handshake
Logic
FIGURE 3-2:
2
STATUS
Digital Section
26 22 23 24 25 21
RUN/ OSC OSC OSC BUFF MODE
HOLD IN OUT SEL OSC
OUT
27
SEND
18
LBEN
19
HBEN
20
CE/LOAD
1
GND
DS21456C-page 10
© 2006 Microchip Technology Inc.