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TDA1314

Quadruple filter DAC

Philips Electronics 

Philips Semiconductors

Quadruple filter DAC

Product specification

TDA1314T

UP-SAMPLE GENERATOR

This block generates the clocks for the up-sample

filters.The external pinning of the 4fas generator block is:

• MCLK (see Fig.4), which is a jitter free (maximum 30 ns

jitter) external clock at any multiple integer from

45 to 128 times 4fas (4 times the frequency of WS) of the

I2S-bus input, thus for a sample frequency of 38 kHz this

clock frequency will range from 6.840 MHz to

19.456 MHz in multiples of 152 kHz.

• The select in-phase (SELINPH) or free running mode of

the synthesizer 45 to 128. In the normal application the

free-running mode is used and this pin is not connected

(this pin is pulled down by an internal resistor). The

phase-locked mode can be selected by hard-wiring this

pin to VDDD (pin 8). However, this mode is

not recommended.

Test interface

This block controls the circuit in the test mode, which can

be either an analog or digital test mode. Test pins TC

(pin 1), AT/DT (pin 2), CMT (pin 23), SCOUT1 (pin 27)

and SCOUT2 (pin 28) are not connected in Fig.6.

Up-sample filter and noise shaper

The signal flow applied to the up-sample filter and noise

shaper blocks is the 4 × 18-bit parallel data words in two's

complement format from the I2S-bus interface at the audio

sampling frequency. The signal flow from these blocks is

the 4 × 15-bit parallel data words in two's complement

format at a frequency of 4fas. Each of the four digital filters

is a four times up-sampling filter. This up-sampling filter is

an elliptic filter of 8th order.

The filters produce an attenuation of 29 dB (min) for

signals outside the audio band. The noise shaper operates

at 4fas and reduces the word length from 22 bits to 15 bits

which is the word length of the DAC.

DAC input signals

The following signals are input to the DAC blocks FL, FR,

RL and RR:

• DATA WORD (bits 10 to 14). These 5 bits are used to

control, via a thermometer decoder, the current of the

32 coarse current sources of the analog DAC part. The

value of this data word determines the total coarse

current flowing to the DAC current output. The value of

the current of each coarse current source is determined

by the following:

Rref; this is the current reference input at pin 14 and is at

the same voltage level as Vref. A resistor connected to

OGND results in a current. This being the reference

current of the coarse current sources and subsequently

of the DAC in total.

• DATA WORD (bits 1 to 9). A current from one of the

coarse current sources is fed into a 512 transistor

matrix. The value of the DATA WORD (bits 1 to 9)

determines which part of one coarse current flows to the

DAC current output.

• DATA WORD (bit 15). This data word MSB controls the

direction of the flow of the DAC output current by

switching the current direction switch.

• Vref. Voltage reference pin internally connected to a

resistor divider to obtain half of the power supply

voltage. This voltage is buffered and used as reference

voltage input for the operational amplifiers and as a

reference voltage in the DAC.

• POWER-UP. The analog signal on this pin controls the

current biasing circuit of the DACs. This pin is connected

internally via a high value resistor to VDDA. Together with

an external capacitor a soft switch-on of the DAC output

currents is obtained. This pin can also be used as the

analog mute input for all DAC output currents by pulling

it to ground.

August 1994

6

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