TDA9151B Ver la hoja de datos (PDF) - Philips Electronics
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TDA9151B Datasheet PDF : 36 Pages
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Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
Table 3 Explanation of control bits shown in Table 2.
CONTROL BITS
LFSS
DINT
BLDS
GBS
VAP
FBL
WS
MS
CSU
PRD
DIP
CPR
VPR
line frame start/stop
de-interlace
bleeder mode selection
guard band selection
polarity of VA edge detection
flyback slicing level
wait state on/off
mode select
clamping suppression mode
protection/detection mode
de-interlace phase
compression on/off
vertical power reduction mode
DESCRIPTION
Table 4 Clock frequency control bit (pin 5; note 1).
CONTROL BIT
LLCS
LOGIC
0
1
FUNCTION
prescaler on: the internal clock frequency fclk = 1⁄2fLLC
prescaler off (default by internal pull-up resistor): the internal clock frequency fclk = fLLC
Note
1. Switching of the prescaler is only allowed when LFSS is LOW. It is highly recommended to hard wire LLCS to ground
or VCC. Active switching may damage the output power transistor due to the changing HOUT pulse. This may cause
very high currents and large flyback pulses. The permitted combinations of LLC and the prescaler are shown in
Table 5.
Table 5 Line duration with prescaler.
LLC (MHz)
6.75
13.5
27
Note
1. Combination not allowed.
ON (µs)
note 1
64
32
OFF (µs)
64
32
note 1
July 1994
8
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