TDA9952 Ver la hoja de datos (PDF) - Philips Electronics

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TDA9952

10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras

Philips Electronics 

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IN

N

N+1

N+2

N+3

N+4

N+5

SHP

0.8 V

tCDS(min)

2.0 V

th(IN;SHP)

SHD

0.8 V

tCDS(min)

0.8 V

2.0 V

th(IN;SHD)

tCLKH

2.0 V

CLK

0.8 V

td(SHD;CLK)

2.0 V

0.8 V

2.0 V

DATA

N−4

N − 3 50%

N−2

N−1

N

ADC CLAMP

CODE

th(o)

td(o)

2.0 V

BLK

tsu(BLK;SHD)

MGU673

SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at falling edge.

Recommended placement for CLK rising edge is between the falling edge of SHD and the rising edge of SHP.

Fig.3 Pixel frequency timing diagram; all polarities active HIGH.

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