TJA1085HN Ver la hoja de datos (PDF) - NXP Semiconductors.
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TJA1085HN Datasheet PDF : 61 Pages
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NXP Semiconductors
TJA1085
FlexRay active star coupler
Table 4.
Bus
DATA_0
DATA_1
idle
X
X
Bus as input
VIO UV RXD
detected
yes
LOW
yes
LOW
yes
LOW
yes
LOW
X
HIGH
TRXD0
TRXD1
Operating mode
LOW
high ohmic[1]
high ohmic[1]
high ohmic[1]
high ohmic[1]
high ohmic[1]
LOW
high ohmic[1]
high ohmic[1]
high ohmic[1]
AS_Normal
AS_Normal
AS_Normal
AS_Standby, AS_Sleep
AS_PowerOff, AS_Reset
[1] Internal pull-up resistor (Rpu) to VBUF.
Table 5. TRXD0/1 interface configured as input
TRXD0
TRXD1
VIO UV
RXD
Bus
detected
X
falling edge no
HIGH
DATA_1
HIGH
HIGH
no
HIGH
idle
falling edge X
X
LOW
DATA_0
X
falling edge yes
LOW
DATA_1
HIGH
HIGH
yes
LOW
idle
LOW
LOW
X
LOW
DATA_0
[1] Activity detected on TRXD0/TRXD1.
Operating mode
AS_Normal[1]
AS_Normal
AS_Normal[1]
AS_Normal[1]
AS_Normal
collision detected on TRXD0/1
6.6 Bus error detection
The TJA1085 provides bus error detection on each branch during data transmission.
When a transmit error (TxE_BRx = 1) is detected on a branch, an EVENT_BRx interrupt is
generated to notify the host.
The following conditions trigger bus error detection:
• Short circuit BP to BM
• Short-circuit BP to GND
• Short-circuit BM to GND
• Short-circuit BP to VCC or VBAT
• Short-circuit BM to VCC or VBAT
6.7 Interrupt generation
Interrupts are generated when specific events take place or associated status bits in the
General or Branch X status registers are set. When an interrupt is generated, the relevant
interrupt status bit is set in the Interrupt Status register (see Table 9) and pin INTN is
forced LOW.
Some interrupt status bits (PWON, WU, SPI_ERROR and HC_ERROR) are reset
immediately after the Interrupt Status register has been read successfully (i.e. a rising
edge on SCSN with no SPI_ERROR).
TJA1085
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 October 2012
© NXP B.V. 2012. All rights reserved.
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