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TMC2242CKTC1

Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz

Fairchild Semiconductor 

PRODUCT SPECIFICATION

TMC2242C

Pin Descriptions

Pin Number

Pin Name PLCC MQFP

Pin Function Description

Dedicated Timing Controls

CLK

42

36

Clock. The chip operates from a single-phase master clock, to whose rising

edges all timing parameters are referenced. All internal registers are strobed on

every rising edge of CLK, although the output register is strobed on alternate

rising edges during decimation. In all modes, the frequency applied to CLK is the

higher of the input and output data sampling rates. During interpolation, the chip

reads its input bus on alternate rising edges of CLK.

SYNC

43

37

Synchronization. During interpolation, the chip accepts input data on alternate

rising edges of CLK and inserts zeroes on the remaining cycles. If SYNC is

HIGH during CLK rising edge 0 and LOW during CLK rising edge 1, the chip will

accept data on CLK 1 and insert a zero on CLK 2. Thereafter, if SYNC is either

held LOW or fed a square wave of half the CLK frequency, the part will continue

to accept data on odd-numbered CLK edges and to stuff zeroes on even-

numbered edges. Similarly, during decimation, the output data change only on

alternate clock cycles. If the user operates SYNC as above, each even-

numbered rising edge of CLK will trigger a change in the output. In all other

modes, the state of SYNC doesn’t affect operation of the chip.

Dedicated Data Input Port

SI11-0

40, 34, Input Data. A 12-bit two’s complement or unsigned input word is registered by

37-30, 31-24, the rising edges of CLK. SI0 is the LSB.

27-25 21-19

Dedicated Data Output Port

SO15-0

4-11,

14-21

42-44,

1-5,

8-15

Output Data MSBs. When OE is LOW, the 12 most significant bits of the filter’s

output emerge here, following each rising edge of CLK. The format may be two’s

complement, unsigned, or inverted offset binary. Bits SO15-4 correspond to

input bits SI11-0, respectively. An on-chip limiter prevents overflows and

underflows in the output data.

Dual Function Data Output/Control Input Pins

SO3-2

SO1

Output Data. These pins serve as data outputs when RND2 is LOW. When

RND2 is HIGH, they become additional filter mode controls (Table 1).

Output Data 2nd LSB. This pin is a data output when RND2-1 are LOW. When

either RND2 or RND1 is HIGH, it becomes an additional rounding control.1

SO0

Output Data LSB. This pin is a data output if and only if all RND bits are LOW.

Otherwise, it augments the data I/O format controls.2

Dedicated Static Controls (Set state before first desired data input.)

INT, DEC

44, 1 38, 39 Interpolate and Decimate. Jointly with SO3-2, these bits select the chip’s

overall operating mode, as discussed earlier in Table 1

TCO

2

40

Output format control. When TCO is HIGH, the output data are in two’s

complement format. When TCO is LOW, they are inverted offset binary, unless

SO0 is HIGH and RND is nonzero, in which case they are unsigned.

RND2-0

22-24 16-18 Round and output tristate. Selects output rounding position and active bus

width 8-16 bits. All outputs at and below the rounding bit position are tristated,

allowing the 4 LSBs to become control inputs.

Active, Asynchronous Control

OE

3

41

Output enable. LOW activates output bus from SO15 down to the effective LSB,

as chosen by RND2-0. All drivers at and below the rounding point are disabled,

as are all drivers when OE is HIGH.

4

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